[PATCH] D100574: [RISCV][WIP] Fix missing emergency slots for scalable stack offsets

[Craig Topper via Phabricator via llvm-commits]

craig.topper added a comment.

Our downstream contains this additional change to reduce the number of virtual registers created

  --- a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
  +++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
  @@ -1353,33 +1353,32 @@ Register RISCVInstrInfo::getVLENFactoredAmount(MachineFunction &MF,
     DebugLoc DL = II->getDebugLoc();
     int64_t NumOfVReg = Amount / 8;
  
  -  Register SizeOfVector = MRI.createVirtualRegister(&RISCV::GPRRegClass);
  -  BuildMI(MBB, II, DL, TII->get(RISCV::PseudoReadVLENB), SizeOfVector);
  -  Register FactorRegister = MRI.createVirtualRegister(&RISCV::GPRRegClass);
  +  Register VL = MRI.createVirtualRegister(&RISCV::GPRRegClass);
  +  BuildMI(MBB, II, DL, TII->get(RISCV::PseudoReadVLENB), VL);
     assert(isInt<12>(NumOfVReg) &&
            "Expect the number of vector registers within 12-bits.");
     if (isPowerOf2_32(NumOfVReg)) {
       uint32_t ShiftAmount = Log2_32(NumOfVReg);
       if (ShiftAmount == 0)
  -      return SizeOfVector;
  -    BuildMI(MBB, II, DL, TII->get(RISCV::SLLI), FactorRegister)
  -        .addReg(SizeOfVector, RegState::Kill)
  +      return VL;
  +    BuildMI(MBB, II, DL, TII->get(RISCV::SLLI), VL)
  +        .addReg(VL)
           .addImm(ShiftAmount);
     } else {
  -    Register VN = MRI.createVirtualRegister(&RISCV::GPRRegClass);
  -    BuildMI(MBB, II, DL, TII->get(RISCV::ADDI), VN)
  +    Register N = MRI.createVirtualRegister(&RISCV::GPRRegClass);
  +    BuildMI(MBB, II, DL, TII->get(RISCV::ADDI), N)
           .addReg(RISCV::X0)
           .addImm(NumOfVReg);
       if (!MF.getSubtarget<RISCVSubtarget>().hasStdExtM())
         MF.getFunction().getContext().diagnose(DiagnosticInfoUnsupported{
             MF.getFunction(),
             "M-extension must be enabled to calculate the vscaled size/offset."});
  -    BuildMI(MBB, II, DL, TII->get(RISCV::MUL), FactorRegister)
  -        .addReg(SizeOfVector, RegState::Kill)
  -        .addReg(VN, RegState::Kill);
  +    BuildMI(MBB, II, DL, TII->get(RISCV::MUL), VL)
  +        .addReg(N, RegState::Kill)
  +        .addReg(VL);
     }
  
  -  return FactorRegister;
  +  return VL;
   }
  
   Optional<std::pair<unsigned, unsigned>>


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D100574/new/

https://reviews.llvm.org/D100574