[PATCH] D100574: [RISCV][WIP] Fix missing emergency slots for scalable stack offsets

[Fraser Cormack via Phabricator via llvm-commits]

frasercrmck added a subscriber: Hsiang-Kai.
frasercrmck added inline comments.


================
Comment at: llvm/test/CodeGen/RISCV/rvv/emergency-slot.mir:92
+    renamable $x13 = nsw ADDI renamable $x16, -2
+    renamable $v0 = PseudoVRELOAD_M1 %stack.1 :: (load unknown-size from %stack.1, align 8)
+    renamable $v0 = PseudoVSLIDEDOWN_VX_M1 undef renamable $v0, killed renamable $v0, killed renamable $x13, $noreg, 8, implicit $vl, implicit $vtype
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>From what I can tell, we need to scavenge three registers to compute the stack offsets at this point. The scalable offsets certainly require two. After adding two extra slots, the code generated is:

```
    renamable $x13 = nsw ADDI renamable $x16, -2
    $x5 = LUI 1
    $x9 = ADDIW killed $x5, -1896
    $x9 = ADD $x2, killed $x9
    $x1 = PseudoReadVLENB
    $x5 = ADDI $x0, 50
    $x1 = MUL killed $x1, killed $x5
    $x5 = LD $x2, 8 :: (load 8 from %stack.17)
    $x9 = ADD killed $x9, killed $x1
    $x1 = LD $x2, 16 :: (load 8 from %stack.16)
    renamable $v0 = PseudoVRELOAD_M1 killed $x9 :: (load unknown-size from %stack.1, align 8)
```

I was wondering if I've missed something in my analysis. Perhaps @rogfer01, @StephenFan or @Hsiang-Kai know more?


Repository:
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  https://reviews.llvm.org/D100574/new/

https://reviews.llvm.org/D100574