[PATCH] D100527: [AArch64][SVE] More unpredicated ld1/st1 patterns for reg+reg addressing modes

[Eli Friedman via Phabricator via llvm-commits]

efriedma created this revision.
efriedma added reviewers: bsmith, paulwalker-arm, peterwaller-arm, joechrisellis.
Herald added subscribers: psnobl, hiraditya, kristof.beyls, tschuett.
efriedma requested review of this revision.
Herald added a project: LLVM.

In some cases, we can improve the generated code by using a load with the "wrong" element width: in particular, using ld1b/st1b when we see reg+reg without a shift.

Patch currently only handles i16; I'll extend it to the other types if the approach seems sound.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D100527

Files:
  llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
  llvm/test/CodeGen/AArch64/named-vector-shuffles-sve.ll
  llvm/test/CodeGen/AArch64/sve-ld1-addressing-mode-reg-reg.ll
  llvm/test/CodeGen/AArch64/sve-st1-addressing-mode-reg-reg.ll

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