[PATCH] D98976: [CodeGen] Use ProcResGroup information in SchedBoundary

[David Penry via Phabricator via llvm-commits]

dpenry added a comment.

I have added a test case which might clarify how the scheduling improves with the scheduler changes; the t2ADDrr is able to dual-issue with VADDD, but VLDRS is not.

But more fundamentally, I am not sure that I'm understanding the semantics of ProcResGroup in the same way, so I'll just ask a few questions...

Assume:

  let BufferSize = 0 in {
     def X : ProcResource<1>;
     def Y : ProcResource<1>; 
     def A : ProcResGroup<[X, Y]>;
  }
  
  def MyWideWrite : SchedWriteRes<[X,Y]> {
    let ResourceCycles = [1, 1];
  }
  
  def MyNarrowWrite: SchedWriteRes[A]> {
    let ResourceCycles = [1];
  }



1. How many instances of A does the scheduling model intend to say that there are: one or two?
2. How many instances of A is MyWideWrite intended to consume?
3. How many instances of A is MyNarrowWrite intended to consume?
4. The goal is to be able to allow two instructions which use MyNarrowWrite to issue together, but to prevent a pair of instructions, one using MyNarrowWrite and the other using MyWideWrite, from dispatching/issuing together.  Is this the right way to represent that restriction?


Repository:
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  https://reviews.llvm.org/D98976/new/

https://reviews.llvm.org/D98976