[llvm] 6401b78 - SDAG: constant fold bf16 -> i16 casts

[Tim Northover via llvm-commits]

Author: Tim Northover
Date: 2021-04-14T11:27:46+01:00
New Revision: 6401b78ab3cf18cb5f0821f9bd52063af0d7ce35

URL: https://github.com/llvm/llvm-project/commit/6401b78ab3cf18cb5f0821f9bd52063af0d7ce35
DIFF: https://github.com/llvm/llvm-project/commit/6401b78ab3cf18cb5f0821f9bd52063af0d7ce35.diff

LOG: SDAG: constant fold bf16 -> i16 casts

This direction is particularly useful because i16 constants are much more
likely to be legal than bf16.

Added: 
    

Modified: 
    llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
    llvm/test/CodeGen/AArch64/bf16.ll

Removed: 
    


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diff  --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index a7989ab73401..71964b3de2b0 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -4642,6 +4642,8 @@ SDValue SelectionDAG::getNode(unsigned Opcode, const SDLoc &DL, EVT VT,
     case ISD::BITCAST:
       if (VT == MVT::i16 && C->getValueType(0) == MVT::f16)
         return getConstant((uint16_t)V.bitcastToAPInt().getZExtValue(), DL, VT);
+      if (VT == MVT::i16 && C->getValueType(0) == MVT::bf16)
+        return getConstant((uint16_t)V.bitcastToAPInt().getZExtValue(), DL, VT);
       else if (VT == MVT::i32 && C->getValueType(0) == MVT::f32)
         return getConstant((uint32_t)V.bitcastToAPInt().getZExtValue(), DL, VT);
       else if (VT == MVT::i64 && C->getValueType(0) == MVT::f64)

diff  --git a/llvm/test/CodeGen/AArch64/bf16.ll b/llvm/test/CodeGen/AArch64/bf16.ll
index f8cedcccdce2..f96919061d74 100644
--- a/llvm/test/CodeGen/AArch64/bf16.ll
+++ b/llvm/test/CodeGen/AArch64/bf16.ll
@@ -36,3 +36,10 @@ entry:
   store <4 x bfloat> %b, <4 x bfloat>* %a, align 16
   ret void
 }
+
+define <8 x bfloat> @test_build_vector_const() {
+; CHECK-LABEL: test_build_vector_const:
+; CHECK: mov [[TMP:w[0-9]+]], #16256
+; CHECK: dup v0.8h, [[TMP]]
+  ret  <8 x bfloat> <bfloat 0xR3F80, bfloat 0xR3F80, bfloat 0xR3F80, bfloat 0xR3F80, bfloat 0xR3F80, bfloat 0xR3F80, bfloat 0xR3F80, bfloat 0xR3F80>
+}