[llvm] 3b32dc4 - [ARM] [COFF] Properly produce cross-section relative relocations

[Martin Storsjö via llvm-commits]

Author: Martin Storsjö
Date: 2021-04-14T12:31:28+03:00
New Revision: 3b32dc4b84c8eaa0de337d6847c2c4cdbfcb4333

URL: https://github.com/llvm/llvm-project/commit/3b32dc4b84c8eaa0de337d6847c2c4cdbfcb4333
DIFF: https://github.com/llvm/llvm-project/commit/3b32dc4b84c8eaa0de337d6847c2c4cdbfcb4333.diff

LOG: [ARM] [COFF] Properly produce cross-section relative relocations

Differential Revision: https://reviews.llvm.org/D99574

Added: 
    

Modified: 
    llvm/lib/Target/ARM/MCTargetDesc/ARMWinCOFFObjectWriter.cpp
    llvm/test/MC/ARM/coff-relocations.s

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/ARM/MCTargetDesc/ARMWinCOFFObjectWriter.cpp b/llvm/lib/Target/ARM/MCTargetDesc/ARMWinCOFFObjectWriter.cpp
index def8ec68f7ff2..31a814900ca50 100644
--- a/llvm/lib/Target/ARM/MCTargetDesc/ARMWinCOFFObjectWriter.cpp
+++ b/llvm/lib/Target/ARM/MCTargetDesc/ARMWinCOFFObjectWriter.cpp
@@ -10,6 +10,7 @@
 #include "llvm/ADT/Twine.h"
 #include "llvm/BinaryFormat/COFF.h"
 #include "llvm/MC/MCAsmBackend.h"
+#include "llvm/MC/MCContext.h"
 #include "llvm/MC/MCExpr.h"
 #include "llvm/MC/MCFixup.h"
 #include "llvm/MC/MCFixupKindInfo.h"
@@ -49,7 +50,17 @@ unsigned ARMWinCOFFObjectWriter::getRelocType(MCContext &Ctx,
   MCSymbolRefExpr::VariantKind Modifier =
     Target.isAbsolute() ? MCSymbolRefExpr::VK_None : Target.getSymA()->getKind();
 
-  switch (static_cast<unsigned>(Fixup.getKind())) {
+  unsigned FixupKind = Fixup.getKind();
+  if (IsCrossSection) {
+    if (FixupKind != FK_Data_4) {
+      Ctx.reportError(Fixup.getLoc(), "Cannot represent this expression");
+      return COFF::IMAGE_REL_ARM_ADDR32;
+    }
+    FixupKind = FK_PCRel_4;
+  }
+
+
+  switch (FixupKind) {
   default: {
     const MCFixupKindInfo &Info = MAB.getFixupKindInfo(Fixup.getKind());
     report_fatal_error(Twine("unsupported relocation type: ") + Info.Name);
@@ -63,6 +74,8 @@ unsigned ARMWinCOFFObjectWriter::getRelocType(MCContext &Ctx,
     default:
       return COFF::IMAGE_REL_ARM_ADDR32;
     }
+  case FK_PCRel_4:
+    return COFF::IMAGE_REL_ARM_REL32;
   case FK_SecRel_2:
     return COFF::IMAGE_REL_ARM_SECTION;
   case FK_SecRel_4:

diff  --git a/llvm/test/MC/ARM/coff-relocations.s b/llvm/test/MC/ARM/coff-relocations.s
index 73211b9ca9019..b2a4a92e5f8cd 100644
--- a/llvm/test/MC/ARM/coff-relocations.s
+++ b/llvm/test/MC/ARM/coff-relocations.s
@@ -4,6 +4,9 @@
 @ RUN: llvm-mc -triple thumbv7-windows-itanium -filetype obj -o - %s \
 @ RUN:   | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-ENCODING
 
+@ RUN: llvm-mc -triple thumbv7-windows-itanium -filetype obj -o - %s \
+@ RUN:   | llvm-objdump -s - | FileCheck %s --check-prefix=CHECK-DATA
+
 	.syntax unified
 	.text
 	.thumb
@@ -87,6 +90,11 @@ secrel:
 .Lsecrel:
 	.long target(secrel32)
 
+	.section .rdata, "dr"
+.Ltable:
+	.word addr32nb - .Ltable
+	.word secrel - .Ltable
+
 @ CHECK-ENCODING-LABEL: <secrel>:
 @ CHECK-ENCODING-NEXT: ldr.w r0, [pc, #4]
 @ CHECK-ENCODING-NEXT: bx r0
@@ -105,5 +113,11 @@ secrel:
 @ CHECK-RELOCATION:     0x2C IMAGE_REL_ARM_ADDR32NB
 @ CHECK-RELOCATION:     0x38 IMAGE_REL_ARM_SECREL
 @ CHECK-RELOCATION:   }
+@ CHECK-RELOCATION:   Section (4) .rdata {
+@ CHECK-RELOCATION:     0x0 IMAGE_REL_ARM_REL32
+@ CHECK-RELOCATION:     0x4 IMAGE_REL_ARM_REL32
+@ CHECK-RELOCATION:   }
 @ CHECK-RELOCATION: ]
 
+@ CHECK-DATA: Contents of section .rdata:
+@ CHECK-DATA-NEXT: 0000 00000000 04000000