[PATCH] D100435: [ARM] Transforming memset to Tail predicated Loop
Dave Green via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Wed Apr 14 01:30:11 PDT 2021
dmgreen added a comment.
Can you base this on top of D99723 <https://reviews.llvm.org/D99723>? Some of the code may be able to be shared, even if there will be differences.
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Comment at: llvm/lib/Target/ARM/ARMISelLowering.cpp:11088
+ Register VdupReg = MRI.createVirtualRegister(&ARM::MQPRRegClass);
+ BuildMI(TpEntry, Dl, TII->get(ARM::MVE_VDUP8))
+ .addDef(VdupReg)
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It might be worth creating a dup in EmitTargetCodeForMemset and having this use the vector value it produced.
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D100435/new/
https://reviews.llvm.org/D100435
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