[PATCH] D100453: [MIR][NFC] Introduce a new method to check a MachineInstr contains implicit register

[Kai Luo via Phabricator via llvm-commits]

lkail created this revision.
lkail added reviewers: arsenm, efriedma, shchenz, nemanjai, jsji, dblaikie.
lkail requested review of this revision.
Herald added subscribers: llvm-commits, wdng.
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The motivation of adding this method is suggestion from @shchenz when reviewing https://reviews.llvm.org/D85288.

When performing peephole optimization, after calling `MI.setDesc` the boundary between explicit operands and implicit operands might be changed, it's not feasible to call `MI.implicit_operands().empty()` to check if the `MI` contains any implicit operand in the mid of constructing a new `MI`.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D100453

Files:
  llvm/include/llvm/CodeGen/MachineInstr.h


Index: llvm/include/llvm/CodeGen/MachineInstr.h
===================================================================
--- llvm/include/llvm/CodeGen/MachineInstr.h
+++ llvm/include/llvm/CodeGen/MachineInstr.h
@@ -1860,6 +1860,12 @@
     AttrOperand.setImm(AttrOperand.getImm() | (uint32_t)Attr);
   }
 
+  bool containsImplicitRegister() const {
+    return any_of(operands(), [](const MachineOperand &MO) {
+      return MO.isReg() && MO.isImplicit();
+    });
+  }
+
 private:
   /// If this instruction is embedded into a MachineFunction, return the
   /// MachineRegisterInfo object for the current function, otherwise


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