[llvm] 1afdfc6 - [RISCV] Rename RISCVISD::GREVI(W)/GORCI(W) to RISCVISD::GREV(W)/GORC(W). Don't require second operand to be a constant.
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Tue Apr 13 11:15:51 PDT 2021
Author: Craig Topper
Date: 2021-04-13T11:04:28-07:00
New Revision: 1afdfc6169bead84f9cbc5dc732b0afa3297f5df
URL: https://github.com/llvm/llvm-project/commit/1afdfc6169bead84f9cbc5dc732b0afa3297f5df
DIFF: https://github.com/llvm/llvm-project/commit/1afdfc6169bead84f9cbc5dc732b0afa3297f5df.diff
LOG: [RISCV] Rename RISCVISD::GREVI(W)/GORCI(W) to RISCVISD::GREV(W)/GORC(W). Don't require second operand to be a constant.
Prep work for adding intrinsics for these instructions in the
future.
Added:
Modified:
llvm/lib/Target/RISCV/RISCVISelLowering.cpp
llvm/lib/Target/RISCV/RISCVISelLowering.h
llvm/lib/Target/RISCV/RISCVInstrInfoB.td
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 7b66509d4119..398366452f72 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -1613,8 +1613,8 @@ SDValue RISCVTargetLowering::LowerOperation(SDValue Op,
// If this is BSWAP rather than BITREVERSE, clear the lower 3 bits.
if (Op.getOpcode() == ISD::BSWAP)
Imm &= ~0x7U;
- return DAG.getNode(RISCVISD::GREVI, DL, VT, Op.getOperand(0),
- DAG.getTargetConstant(Imm, DL, Subtarget.getXLenVT()));
+ return DAG.getNode(RISCVISD::GREV, DL, VT, Op.getOperand(0),
+ DAG.getConstant(Imm, DL, VT));
}
case ISD::FSHL:
case ISD::FSHR: {
@@ -2898,8 +2898,8 @@ SDValue RISCVTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
}
case Intrinsic::riscv_orc_b:
// Lower to the GORCI encoding for orc.b.
- return DAG.getNode(RISCVISD::GORCI, DL, XLenVT, Op.getOperand(1),
- DAG.getTargetConstant(7, DL, XLenVT));
+ return DAG.getNode(RISCVISD::GORC, DL, XLenVT, Op.getOperand(1),
+ DAG.getConstant(7, DL, XLenVT));
case Intrinsic::riscv_vmv_x_s:
assert(Op.getValueType() == XLenVT && "Unexpected VT!");
return DAG.getNode(RISCVISD::VMV_X_S, DL, Op.getValueType(),
@@ -4018,10 +4018,10 @@ static RISCVISD::NodeType getRISCVWOpcode(unsigned Opcode) {
return RISCVISD::ROLW;
case ISD::ROTR:
return RISCVISD::RORW;
- case RISCVISD::GREVI:
- return RISCVISD::GREVIW;
- case RISCVISD::GORCI:
- return RISCVISD::GORCIW;
+ case RISCVISD::GREV:
+ return RISCVISD::GREVW;
+ case RISCVISD::GORC:
+ return RISCVISD::GORCW;
}
}
@@ -4279,18 +4279,20 @@ void RISCVTargetLowering::ReplaceNodeResults(SDNode *N,
}
break;
}
- case RISCVISD::GREVI:
- case RISCVISD::GORCI: {
+ case RISCVISD::GREV:
+ case RISCVISD::GORC: {
assert(N->getValueType(0) == MVT::i32 && Subtarget.is64Bit() &&
"Unexpected custom legalisation");
+ assert(isa<ConstantSDNode>(N->getOperand(1)) && "Expected constant");
// This is similar to customLegalizeToWOp, except that we pass the second
// operand (a TargetConstant) straight through: it is already of type
// XLenVT.
RISCVISD::NodeType WOpcode = getRISCVWOpcode(N->getOpcode());
SDValue NewOp0 =
DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, N->getOperand(0));
- SDValue NewRes =
- DAG.getNode(WOpcode, DL, MVT::i64, NewOp0, N->getOperand(1));
+ SDValue NewOp1 =
+ DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, N->getOperand(1));
+ SDValue NewRes = DAG.getNode(WOpcode, DL, MVT::i64, NewOp0, NewOp1);
// ReplaceNodeResults requires we maintain the same type for the return
// value.
Results.push_back(DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, NewRes));
@@ -4318,9 +4320,8 @@ void RISCVTargetLowering::ReplaceNodeResults(SDNode *N,
SDValue NewOp0 = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64,
N->getOperand(0));
unsigned Imm = N->getOpcode() == ISD::BITREVERSE ? 31 : 24;
- SDValue GREVIW = DAG.getNode(RISCVISD::GREVIW, DL, MVT::i64, NewOp0,
- DAG.getTargetConstant(Imm, DL,
- Subtarget.getXLenVT()));
+ SDValue GREVIW = DAG.getNode(RISCVISD::GREVW, DL, MVT::i64, NewOp0,
+ DAG.getConstant(Imm, DL, MVT::i64));
// ReplaceNodeResults requires we maintain the same type for the return
// value.
Results.push_back(DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, GREVIW));
@@ -4416,9 +4417,9 @@ void RISCVTargetLowering::ReplaceNodeResults(SDNode *N,
DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, N->getOperand(1));
// If Zbp is enabled, use GORCIW which will sign extend the result.
unsigned Opc =
- Subtarget.hasStdExtZbp() ? RISCVISD::GORCIW : RISCVISD::GORCI;
+ Subtarget.hasStdExtZbp() ? RISCVISD::GORCW : RISCVISD::GORC;
SDValue Res = DAG.getNode(Opc, DL, MVT::i64, NewOp,
- DAG.getTargetConstant(7, DL, MVT::i64));
+ DAG.getConstant(7, DL, MVT::i64));
Results.push_back(DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Res));
return;
}
@@ -4599,9 +4600,8 @@ static SDValue combineORToGREV(SDValue Op, SelectionDAG &DAG,
auto RHS = matchGREVIPat(Op.getOperand(1));
if (LHS && RHS && LHS->formsPairWith(*RHS)) {
SDLoc DL(Op);
- return DAG.getNode(
- RISCVISD::GREVI, DL, VT, LHS->Op,
- DAG.getTargetConstant(LHS->ShAmt, DL, Subtarget.getXLenVT()));
+ return DAG.getNode(RISCVISD::GREV, DL, VT, LHS->Op,
+ DAG.getConstant(LHS->ShAmt, DL, VT));
}
}
return SDValue();
@@ -4627,9 +4627,10 @@ static SDValue combineORToGORC(SDValue Op, SelectionDAG &DAG,
SDValue Op1 = Op.getOperand(1);
auto MatchOROfReverse = [&](SDValue Reverse, SDValue X) {
- if (Reverse.getOpcode() == RISCVISD::GREVI && Reverse.getOperand(0) == X &&
+ if (Reverse.getOpcode() == RISCVISD::GREV && Reverse.getOperand(0) == X &&
+ isa<ConstantSDNode>(Reverse.getOperand(1)) &&
isPowerOf2_32(Reverse.getConstantOperandVal(1)))
- return DAG.getNode(RISCVISD::GORCI, DL, VT, X, Reverse.getOperand(1));
+ return DAG.getNode(RISCVISD::GORC, DL, VT, X, Reverse.getOperand(1));
// We can also form GORCI from ROTL/ROTR by half the bitwidth.
if ((Reverse.getOpcode() == ISD::ROTL ||
Reverse.getOpcode() == ISD::ROTR) &&
@@ -4637,9 +4638,8 @@ static SDValue combineORToGORC(SDValue Op, SelectionDAG &DAG,
isa<ConstantSDNode>(Reverse.getOperand(1))) {
uint64_t RotAmt = Reverse.getConstantOperandVal(1);
if (RotAmt == (VT.getSizeInBits() / 2))
- return DAG.getNode(
- RISCVISD::GORCI, DL, VT, X,
- DAG.getTargetConstant(RotAmt, DL, Subtarget.getXLenVT()));
+ return DAG.getNode(RISCVISD::GORC, DL, VT, X,
+ DAG.getConstant(RotAmt, DL, VT));
}
return SDValue();
};
@@ -4666,9 +4666,8 @@ static SDValue combineORToGORC(SDValue Op, SelectionDAG &DAG,
}
auto RHS = matchGREVIPat(Op1);
if (LHS && RHS && LHS->formsPairWith(*RHS) && LHS->Op == OrOp1) {
- return DAG.getNode(
- RISCVISD::GORCI, DL, VT, LHS->Op,
- DAG.getTargetConstant(LHS->ShAmt, DL, Subtarget.getXLenVT()));
+ return DAG.getNode(RISCVISD::GORC, DL, VT, LHS->Op,
+ DAG.getConstant(LHS->ShAmt, DL, VT));
}
}
return SDValue();
@@ -4774,17 +4773,21 @@ static SDValue combineORToSHFL(SDValue Op, SelectionDAG &DAG,
// Combine (GORCI (GORCI x, C2), C1) -> (GORCI x, C1|C2). Repeated stage does
// not undo itself, but they are redundant.
static SDValue combineGREVI_GORCI(SDNode *N, SelectionDAG &DAG) {
- unsigned ShAmt1 = N->getConstantOperandVal(1);
SDValue Src = N->getOperand(0);
if (Src.getOpcode() != N->getOpcode())
return SDValue();
+ if (!isa<ConstantSDNode>(N->getOperand(1)) ||
+ !isa<ConstantSDNode>(Src.getOperand(1)))
+ return SDValue();
+
+ unsigned ShAmt1 = N->getConstantOperandVal(1);
unsigned ShAmt2 = Src.getConstantOperandVal(1);
Src = Src.getOperand(0);
unsigned CombinedShAmt;
- if (N->getOpcode() == RISCVISD::GORCI || N->getOpcode() == RISCVISD::GORCIW)
+ if (N->getOpcode() == RISCVISD::GORC || N->getOpcode() == RISCVISD::GORCW)
CombinedShAmt = ShAmt1 | ShAmt2;
else
CombinedShAmt = ShAmt1 ^ ShAmt2;
@@ -4793,9 +4796,9 @@ static SDValue combineGREVI_GORCI(SDNode *N, SelectionDAG &DAG) {
return Src;
SDLoc DL(N);
- return DAG.getNode(N->getOpcode(), DL, N->getValueType(0), Src,
- DAG.getTargetConstant(CombinedShAmt, DL,
- N->getOperand(1).getValueType()));
+ return DAG.getNode(
+ N->getOpcode(), DL, N->getValueType(0), Src,
+ DAG.getConstant(CombinedShAmt, DL, N->getOperand(1).getValueType()));
}
SDValue RISCVTargetLowering::PerformDAGCombine(SDNode *N,
@@ -4909,8 +4912,8 @@ SDValue RISCVTargetLowering::PerformDAGCombine(SDNode *N,
}
break;
}
- case RISCVISD::GREVIW:
- case RISCVISD::GORCIW: {
+ case RISCVISD::GREVW:
+ case RISCVISD::GORCW: {
// Only the lower 32 bits of the first operand are read
SDValue Op0 = N->getOperand(0);
APInt Mask = APInt::getLowBitsSet(Op0.getValueSizeInBits(), 32);
@@ -4952,8 +4955,8 @@ SDValue RISCVTargetLowering::PerformDAGCombine(SDNode *N,
return DAG.getNode(ISD::AND, DL, MVT::i64, NewFMV,
DAG.getConstant(~SignBit, DL, MVT::i64));
}
- case RISCVISD::GREVI:
- case RISCVISD::GORCI:
+ case RISCVISD::GREV:
+ case RISCVISD::GORC:
return combineGREVI_GORCI(N, DCI.DAG);
case ISD::OR:
if (auto GREV = combineORToGREV(SDValue(N, 0), DCI.DAG, Subtarget))
@@ -5360,8 +5363,8 @@ unsigned RISCVTargetLowering::ComputeNumSignBitsForTargetNode(
case RISCVISD::REMUW:
case RISCVISD::ROLW:
case RISCVISD::RORW:
- case RISCVISD::GREVIW:
- case RISCVISD::GORCIW:
+ case RISCVISD::GREVW:
+ case RISCVISD::GORCW:
case RISCVISD::FSLW:
case RISCVISD::FSRW:
// TODO: As the result is sign-extended, this is conservatively correct. A
@@ -7105,10 +7108,10 @@ const char *RISCVTargetLowering::getTargetNodeName(unsigned Opcode) const {
NODE_NAME_CASE(FMV_W_X_RV64)
NODE_NAME_CASE(FMV_X_ANYEXTW_RV64)
NODE_NAME_CASE(READ_CYCLE_WIDE)
- NODE_NAME_CASE(GREVI)
- NODE_NAME_CASE(GREVIW)
- NODE_NAME_CASE(GORCI)
- NODE_NAME_CASE(GORCIW)
+ NODE_NAME_CASE(GREV)
+ NODE_NAME_CASE(GREVW)
+ NODE_NAME_CASE(GORC)
+ NODE_NAME_CASE(GORCW)
NODE_NAME_CASE(SHFL)
NODE_NAME_CASE(VMV_V_X_VL)
NODE_NAME_CASE(VFMV_V_F_VL)
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.h b/llvm/lib/Target/RISCV/RISCVISelLowering.h
index 6bc64717bcd8..2cf7e53d49da 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.h
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.h
@@ -89,13 +89,12 @@ enum NodeType : unsigned {
// Generalized Reverse and Generalized Or-Combine - directly matching the
// semantics of the named RISC-V instructions. Lowered as custom nodes as
// TableGen chokes when faced with commutative permutations in deeply-nested
- // DAGs. Each node takes an input operand and a TargetConstant immediate
- // shift amount, and outputs a bit-manipulated version of input. All operands
- // are of type XLenVT.
- GREVI,
- GREVIW,
- GORCI,
- GORCIW,
+ // DAGs. Each node takes an input operand and a control operand and outputs a
+ // bit-manipulated version of input. All operands are i32 or XLenVT.
+ GREV,
+ GREVW,
+ GORC,
+ GORCW,
SHFL,
// Vector Extension
// VMV_V_X_VL matches the semantics of vmv.v.x but includes an extra operand
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoB.td b/llvm/lib/Target/RISCV/RISCVInstrInfoB.td
index 6890a483d4a3..b92fbb7d7ab4 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoB.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoB.td
@@ -25,10 +25,10 @@ def riscv_fslw : SDNode<"RISCVISD::FSLW", SDT_RISCVIntShiftDOpW>;
def riscv_fsrw : SDNode<"RISCVISD::FSRW", SDT_RISCVIntShiftDOpW>;
def riscv_fsl : SDNode<"RISCVISD::FSL", SDTIntShiftDOp>;
def riscv_fsr : SDNode<"RISCVISD::FSR", SDTIntShiftDOp>;
-def riscv_grevi : SDNode<"RISCVISD::GREVI", SDTIntBinOp>;
-def riscv_greviw : SDNode<"RISCVISD::GREVIW", SDT_RISCVIntBinOpW>;
-def riscv_gorci : SDNode<"RISCVISD::GORCI", SDTIntBinOp>;
-def riscv_gorciw : SDNode<"RISCVISD::GORCIW", SDT_RISCVIntBinOpW>;
+def riscv_grev : SDNode<"RISCVISD::GREV", SDTIntBinOp>;
+def riscv_grevw : SDNode<"RISCVISD::GREVW", SDT_RISCVIntBinOpW>;
+def riscv_gorc : SDNode<"RISCVISD::GORC", SDTIntBinOp>;
+def riscv_gorcw : SDNode<"RISCVISD::GORCW", SDT_RISCVIntBinOpW>;
def riscv_shfl : SDNode<"RISCVISD::SHFL", SDTIntBinOp>;
def UImmLog2XLenHalfAsmOperand : AsmOperandClass {
@@ -719,27 +719,29 @@ def : Pat<(rotl GPR:$rs1, uimmlog2xlen:$shamt),
// We treat orc.b as a separate instruction, so match it directly. We also
// lower the Zbb orc.b intrinsic to this.
-def : Pat<(riscv_gorci GPR:$rs1, 7), (ORCB GPR:$rs1)>;
+def : Pat<(riscv_gorc GPR:$rs1, 7), (ORCB GPR:$rs1)>;
}
let Predicates = [HasStdExtZbp] in {
def : Pat<(riscv_shfl GPR:$rs1, shfl_uimm:$shamt),
(SHFLI GPR:$rs1, shfl_uimm:$shamt)>;
-def : Pat<(riscv_grevi GPR:$rs1, timm:$shamt), (GREVI GPR:$rs1, timm:$shamt)>;
-def : Pat<(riscv_gorci GPR:$rs1, timm:$shamt), (GORCI GPR:$rs1, timm:$shamt)>;
+def : Pat<(riscv_grev GPR:$rs1, uimmlog2xlen:$shamt),
+ (GREVI GPR:$rs1, uimmlog2xlen:$shamt)>;
+def : Pat<(riscv_gorc GPR:$rs1, uimmlog2xlen:$shamt),
+ (GORCI GPR:$rs1, uimmlog2xlen:$shamt)>;
} // Predicates = [HasStdExtZbp]
let Predicates = [HasStdExtZbp, IsRV32] in {
-def : Pat<(i32 (rotr (riscv_grevi GPR:$rs1, 24), (i32 16))), (GREVI GPR:$rs1, 8)>;
-def : Pat<(i32 (rotl (riscv_grevi GPR:$rs1, 24), (i32 16))), (GREVI GPR:$rs1, 8)>;
+def : Pat<(i32 (rotr (riscv_grev GPR:$rs1, 24), (i32 16))), (GREVI GPR:$rs1, 8)>;
+def : Pat<(i32 (rotl (riscv_grev GPR:$rs1, 24), (i32 16))), (GREVI GPR:$rs1, 8)>;
// We treat rev8 as a separate instruction, so match it directly.
-def : Pat<(i32 (riscv_grevi GPR:$rs1, 24)), (REV8_RV32 GPR:$rs1)>;
+def : Pat<(i32 (riscv_grev GPR:$rs1, 24)), (REV8_RV32 GPR:$rs1)>;
} // Predicates = [HasStdExtZbp, IsRV32]
let Predicates = [HasStdExtZbp, IsRV64] in {
// We treat rev8 as a separate instruction, so match it directly.
-def : Pat<(i64 (riscv_grevi GPR:$rs1, 56)), (REV8_RV64 GPR:$rs1)>;
+def : Pat<(i64 (riscv_grev GPR:$rs1, 56)), (REV8_RV64 GPR:$rs1)>;
} // Predicates = [HasStdExtZbp, IsRV64]
let Predicates = [HasStdExtZbt] in {
@@ -883,10 +885,10 @@ def : Pat<(riscv_rolw GPR:$rs1, uimm5:$rs2),
} // Predicates = [HasStdExtZbbOrZbp, IsRV64]
let Predicates = [HasStdExtZbp, IsRV64] in {
-def : Pat<(riscv_rorw (riscv_greviw GPR:$rs1, 24), 16), (GREVIW GPR:$rs1, 8)>;
-def : Pat<(riscv_rolw (riscv_greviw GPR:$rs1, 24), 16), (GREVIW GPR:$rs1, 8)>;
-def : Pat<(riscv_greviw GPR:$rs1, timm:$shamt), (GREVIW GPR:$rs1, timm:$shamt)>;
-def : Pat<(riscv_gorciw GPR:$rs1, timm:$shamt), (GORCIW GPR:$rs1, timm:$shamt)>;
+def : Pat<(riscv_rorw (riscv_grevw GPR:$rs1, 24), 16), (GREVIW GPR:$rs1, 8)>;
+def : Pat<(riscv_rolw (riscv_grevw GPR:$rs1, 24), 16), (GREVIW GPR:$rs1, 8)>;
+def : Pat<(riscv_grevw GPR:$rs1, uimm5:$shamt), (GREVIW GPR:$rs1, uimm5:$shamt)>;
+def : Pat<(riscv_gorcw GPR:$rs1, uimm5:$shamt), (GORCIW GPR:$rs1, uimm5:$shamt)>;
} // Predicates = [HasStdExtZbp, IsRV64]
let Predicates = [HasStdExtZbt, IsRV64] in {
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