[PATCH] D100398: [AArch64][GlobalISel] Regbankselect + select @llvm.aarch64.neon.uaddlv

[Jessica Paquette via Phabricator via llvm-commits]

paquette created this revision.
paquette added a reviewer: aemerson.
Herald added subscribers: danielkiss, hiraditya, kristof.beyls, rovka.
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Herald added a project: LLVM.

It turns out we actually import a bunch of selection code for intrinsics. The imported code checks that the register banks on the G_INTRINSIC instruction are correct. If so, it goes ahead and selects it.

This adds code to AArch64RegisterBankInfo to allow us to correctly determine register banks on intrinsics which have known register bank constraints.

For now, this only handles `@llvm.aarch64.neon.uaddlv`. This is necessary for porting `AArch64TargetLowering::LowerCTPOP`.

Also add a utility for getting the intrinsic ID from a G_INTRINSIC instruction. This seems a little nicer than having to know about how intrinsic instructions are structured.


https://reviews.llvm.org/D100398

Files:
  llvm/include/llvm/CodeGen/GlobalISel/Utils.h
  llvm/lib/CodeGen/GlobalISel/Utils.cpp
  llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp
  llvm/test/CodeGen/AArch64/GlobalISel/regbank-intrinsic.mir
  llvm/test/CodeGen/AArch64/GlobalISel/select-intrinsic-uaddlv.mir

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