[llvm] bd86824 - [TTI] NFC: Change getArithmeticReductionCost to return InstructionCost
Sander de Smalen via llvm-commits
llvm-commits at lists.llvm.org
Tue Apr 13 06:21:23 PDT 2021
Author: Sander de Smalen
Date: 2021-04-13T14:20:59+01:00
New Revision: bd86824d9865bea90770abd94076f7ba44a33473
URL: https://github.com/llvm/llvm-project/commit/bd86824d9865bea90770abd94076f7ba44a33473
DIFF: https://github.com/llvm/llvm-project/commit/bd86824d9865bea90770abd94076f7ba44a33473.diff
LOG: [TTI] NFC: Change getArithmeticReductionCost to return InstructionCost
This patch migrates the TTI cost interfaces to return an InstructionCost.
See this patch for the introduction of the type: https://reviews.llvm.org/D91174
See this thread for context: http://lists.llvm.org/pipermail/llvm-dev/2020-November/146408.html
This patch is practically NFC, with the exception of an AArch64 SVE related
cost-model change, where we can now return an Invalid cost instead of some
bogus number.
Reviewed By: dmgreen
Differential Revision: https://reviews.llvm.org/D100201
Added:
Modified:
llvm/include/llvm/Analysis/TargetTransformInfo.h
llvm/include/llvm/Analysis/TargetTransformInfoImpl.h
llvm/include/llvm/CodeGen/BasicTTIImpl.h
llvm/lib/Analysis/TargetTransformInfo.cpp
llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
llvm/lib/Target/AArch64/AArch64TargetTransformInfo.h
llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp
llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.h
llvm/lib/Target/ARM/ARMTargetTransformInfo.cpp
llvm/lib/Target/ARM/ARMTargetTransformInfo.h
llvm/lib/Target/X86/X86TargetTransformInfo.cpp
llvm/lib/Target/X86/X86TargetTransformInfo.h
llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
llvm/test/Analysis/CostModel/AArch64/sve-intrinsics.ll
Removed:
################################################################################
diff --git a/llvm/include/llvm/Analysis/TargetTransformInfo.h b/llvm/include/llvm/Analysis/TargetTransformInfo.h
index 3d831acc559f9..cca4a9f0ea43c 100644
--- a/llvm/include/llvm/Analysis/TargetTransformInfo.h
+++ b/llvm/include/llvm/Analysis/TargetTransformInfo.h
@@ -1182,9 +1182,9 @@ class TargetTransformInfo {
/// Split:
/// (v0, v1, v2, v3)
/// ((v0+v2), (v1+v3), undef, undef)
- int getArithmeticReductionCost(
- unsigned Opcode, VectorType *Ty, bool IsPairwiseForm,
- TTI::TargetCostKind CostKind = TTI::TCK_RecipThroughput) const;
+ InstructionCost getArithmeticReductionCost(
+ unsigned Opcode, VectorType *Ty, bool IsPairwiseForm,
+ TTI::TargetCostKind CostKind = TTI::TCK_RecipThroughput) const;
int getMinMaxReductionCost(
VectorType *Ty, VectorType *CondTy, bool IsPairwiseForm, bool IsUnsigned,
@@ -1606,9 +1606,10 @@ class TargetTransformInfo::Concept {
unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef<unsigned> Indices,
Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind,
bool UseMaskForCond = false, bool UseMaskForGaps = false) = 0;
- virtual int getArithmeticReductionCost(unsigned Opcode, VectorType *Ty,
- bool IsPairwiseForm,
- TTI::TargetCostKind CostKind) = 0;
+ virtual InstructionCost
+ getArithmeticReductionCost(unsigned Opcode, VectorType *Ty,
+ bool IsPairwiseForm,
+ TTI::TargetCostKind CostKind) = 0;
virtual int getMinMaxReductionCost(VectorType *Ty, VectorType *CondTy,
bool IsPairwiseForm, bool IsUnsigned,
TTI::TargetCostKind CostKind) = 0;
@@ -2096,9 +2097,10 @@ class TargetTransformInfo::Model final : public TargetTransformInfo::Concept {
Alignment, AddressSpace, CostKind,
UseMaskForCond, UseMaskForGaps);
}
- int getArithmeticReductionCost(unsigned Opcode, VectorType *Ty,
- bool IsPairwiseForm,
- TTI::TargetCostKind CostKind) override {
+ InstructionCost
+ getArithmeticReductionCost(unsigned Opcode, VectorType *Ty,
+ bool IsPairwiseForm,
+ TTI::TargetCostKind CostKind) override {
return Impl.getArithmeticReductionCost(Opcode, Ty, IsPairwiseForm,
CostKind);
}
diff --git a/llvm/include/llvm/Analysis/TargetTransformInfoImpl.h b/llvm/include/llvm/Analysis/TargetTransformInfoImpl.h
index a2971612fbe87..2fae1b04f2be0 100644
--- a/llvm/include/llvm/Analysis/TargetTransformInfoImpl.h
+++ b/llvm/include/llvm/Analysis/TargetTransformInfoImpl.h
@@ -616,8 +616,8 @@ class TargetTransformInfoImplBase {
return 0;
}
- unsigned getArithmeticReductionCost(unsigned, VectorType *, bool,
- TTI::TargetCostKind) const {
+ InstructionCost getArithmeticReductionCost(unsigned, VectorType *, bool,
+ TTI::TargetCostKind) const {
return 1;
}
diff --git a/llvm/include/llvm/CodeGen/BasicTTIImpl.h b/llvm/include/llvm/CodeGen/BasicTTIImpl.h
index 817368261472b..b9dc320d91aba 100644
--- a/llvm/include/llvm/CodeGen/BasicTTIImpl.h
+++ b/llvm/include/llvm/CodeGen/BasicTTIImpl.h
@@ -1937,9 +1937,9 @@ class BasicTTIImplBase : public TargetTransformInfoImplCRTPBase<T> {
///
/// The cost model should take into account that the actual length of the
/// vector is reduced on each iteration.
- unsigned getArithmeticReductionCost(unsigned Opcode, VectorType *Ty,
- bool IsPairwise,
- TTI::TargetCostKind CostKind) {
+ InstructionCost getArithmeticReductionCost(unsigned Opcode, VectorType *Ty,
+ bool IsPairwise,
+ TTI::TargetCostKind CostKind) {
Type *ScalarTy = Ty->getElementType();
unsigned NumVecElts = cast<FixedVectorType>(Ty)->getNumElements();
if ((Opcode == Instruction::Or || Opcode == Instruction::And) &&
@@ -1952,10 +1952,8 @@ class BasicTTIImplBase : public TargetTransformInfoImplCRTPBase<T> {
// %val = bitcast <ReduxWidth x i1> to iReduxWidth
// %res = cmp eq iReduxWidth %val, 11111
Type *ValTy = IntegerType::get(Ty->getContext(), NumVecElts);
- return *thisT()
- ->getCastInstrCost(Instruction::BitCast, ValTy, Ty,
- TTI::CastContextHint::None, CostKind)
- .getValue() +
+ return thisT()->getCastInstrCost(Instruction::BitCast, ValTy, Ty,
+ TTI::CastContextHint::None, CostKind) +
thisT()->getCmpSelInstrCost(Instruction::ICmp, ValTy,
CmpInst::makeCmpResultType(ValTy),
CmpInst::BAD_ICMP_PREDICATE, CostKind);
@@ -2075,7 +2073,7 @@ class BasicTTIImplBase : public TargetTransformInfoImplCRTPBase<T> {
// Without any native support, this is equivalent to the cost of
// vecreduce.add(ext) or if IsMLA vecreduce.add(mul(ext, ext))
VectorType *ExtTy = VectorType::get(ResTy, Ty);
- unsigned RedCost = thisT()->getArithmeticReductionCost(
+ InstructionCost RedCost = thisT()->getArithmeticReductionCost(
Instruction::Add, ExtTy, false, CostKind);
InstructionCost MulCost = 0;
InstructionCost ExtCost = thisT()->getCastInstrCost(
diff --git a/llvm/lib/Analysis/TargetTransformInfo.cpp b/llvm/lib/Analysis/TargetTransformInfo.cpp
index 1d22ebd8866db..93e09e0fae9f7 100644
--- a/llvm/lib/Analysis/TargetTransformInfo.cpp
+++ b/llvm/lib/Analysis/TargetTransformInfo.cpp
@@ -893,12 +893,11 @@ int TargetTransformInfo::getMemcpyCost(const Instruction *I) const {
return Cost;
}
-int TargetTransformInfo::getArithmeticReductionCost(unsigned Opcode,
- VectorType *Ty,
- bool IsPairwiseForm,
- TTI::TargetCostKind CostKind) const {
- int Cost = TTIImpl->getArithmeticReductionCost(Opcode, Ty, IsPairwiseForm,
- CostKind);
+InstructionCost TargetTransformInfo::getArithmeticReductionCost(
+ unsigned Opcode, VectorType *Ty, bool IsPairwiseForm,
+ TTI::TargetCostKind CostKind) const {
+ InstructionCost Cost =
+ TTIImpl->getArithmeticReductionCost(Opcode, Ty, IsPairwiseForm, CostKind);
assert(Cost >= 0 && "TTI should not produce negative costs!");
return Cost;
}
diff --git a/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp b/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
index 33648d947405b..c8207442aaf6b 100644
--- a/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
+++ b/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
@@ -1271,7 +1271,7 @@ int AArch64TTIImpl::getMinMaxReductionCost(VectorType *Ty, VectorType *CondTy,
return LegalizationCost + /*Cost of horizontal reduction*/ 2;
}
-int AArch64TTIImpl::getArithmeticReductionCostSVE(
+InstructionCost AArch64TTIImpl::getArithmeticReductionCostSVE(
unsigned Opcode, VectorType *ValTy, bool IsPairwise,
TTI::TargetCostKind CostKind) {
assert(!IsPairwise && "Cannot be pair wise to continue");
@@ -1295,16 +1295,14 @@ int AArch64TTIImpl::getArithmeticReductionCostSVE(
case ISD::FADD:
return LegalizationCost + 2;
default:
- // TODO: Replace for invalid when InstructionCost is used
- // cases not supported by SVE
- return 16;
+ return InstructionCost::getInvalid();
}
}
-int AArch64TTIImpl::getArithmeticReductionCost(unsigned Opcode,
- VectorType *ValTy,
- bool IsPairwiseForm,
- TTI::TargetCostKind CostKind) {
+InstructionCost
+AArch64TTIImpl::getArithmeticReductionCost(unsigned Opcode, VectorType *ValTy,
+ bool IsPairwiseForm,
+ TTI::TargetCostKind CostKind) {
if (isa<ScalableVectorType>(ValTy))
return getArithmeticReductionCostSVE(Opcode, ValTy, IsPairwiseForm,
diff --git a/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.h b/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.h
index fc02437c6b648..1c397afd405a9 100644
--- a/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.h
+++ b/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.h
@@ -150,9 +150,10 @@ class AArch64TTIImpl : public BasicTTIImplBase<AArch64TTIImpl> {
bool IsPairwise, bool IsUnsigned,
TTI::TargetCostKind CostKind);
- int getArithmeticReductionCostSVE(unsigned Opcode, VectorType *ValTy,
- bool IsPairwiseForm,
- TTI::TargetCostKind CostKind);
+ InstructionCost getArithmeticReductionCostSVE(unsigned Opcode,
+ VectorType *ValTy,
+ bool IsPairwiseForm,
+ TTI::TargetCostKind CostKind);
int getArithmeticInstrCost(
unsigned Opcode, Type *Ty,
@@ -278,9 +279,9 @@ class AArch64TTIImpl : public BasicTTIImplBase<AArch64TTIImpl> {
bool isLegalToVectorizeReduction(RecurrenceDescriptor RdxDesc,
ElementCount VF) const;
- int getArithmeticReductionCost(unsigned Opcode, VectorType *Ty,
- bool IsPairwiseForm,
- TTI::TargetCostKind CostKind = TTI::TCK_RecipThroughput);
+ InstructionCost getArithmeticReductionCost(
+ unsigned Opcode, VectorType *Ty, bool IsPairwiseForm,
+ TTI::TargetCostKind CostKind = TTI::TCK_RecipThroughput);
int getShuffleCost(TTI::ShuffleKind Kind, VectorType *Tp, ArrayRef<int> Mask,
int Index, VectorType *SubTp);
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp
index ac5df7198825b..d69ae79a93403 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp
@@ -846,9 +846,10 @@ unsigned GCNTTIImpl::getCFInstrCost(unsigned Opcode,
return BaseT::getCFInstrCost(Opcode, CostKind, I);
}
-int GCNTTIImpl::getArithmeticReductionCost(unsigned Opcode, VectorType *Ty,
- bool IsPairwise,
- TTI::TargetCostKind CostKind) {
+InstructionCost
+GCNTTIImpl::getArithmeticReductionCost(unsigned Opcode, VectorType *Ty,
+ bool IsPairwise,
+ TTI::TargetCostKind CostKind) {
EVT OrigTy = TLI->getValueType(DL, Ty);
// Computes cost on targets that have packed math instructions(which support
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.h b/llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.h
index a462dd9f02ca2..16cf49e70a7f0 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.h
+++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.h
@@ -209,10 +209,8 @@ class GCNTTIImpl final : public BasicTTIImplBase<GCNTTIImpl> {
int getInlinerVectorBonusPercent() { return 0; }
- int getArithmeticReductionCost(
- unsigned Opcode,
- VectorType *Ty,
- bool IsPairwise,
+ InstructionCost getArithmeticReductionCost(
+ unsigned Opcode, VectorType *Ty, bool IsPairwise,
TTI::TargetCostKind CostKind = TTI::TCK_RecipThroughput);
InstructionCost getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA,
diff --git a/llvm/lib/Target/ARM/ARMTargetTransformInfo.cpp b/llvm/lib/Target/ARM/ARMTargetTransformInfo.cpp
index 5b407609577d5..c0d5e90b8c184 100644
--- a/llvm/lib/Target/ARM/ARMTargetTransformInfo.cpp
+++ b/llvm/lib/Target/ARM/ARMTargetTransformInfo.cpp
@@ -1584,9 +1584,10 @@ InstructionCost ARMTTIImpl::getGatherScatterOpCost(
return ScalarCost;
}
-int ARMTTIImpl::getArithmeticReductionCost(unsigned Opcode, VectorType *ValTy,
- bool IsPairwiseForm,
- TTI::TargetCostKind CostKind) {
+InstructionCost
+ARMTTIImpl::getArithmeticReductionCost(unsigned Opcode, VectorType *ValTy,
+ bool IsPairwiseForm,
+ TTI::TargetCostKind CostKind) {
EVT ValVT = TLI->getValueType(DL, ValTy);
int ISD = TLI->InstructionOpcodeToISD(Opcode);
if (!ST->hasMVEIntegerOps() || !ValVT.isSimple() || ISD != ISD::ADD)
diff --git a/llvm/lib/Target/ARM/ARMTargetTransformInfo.h b/llvm/lib/Target/ARM/ARMTargetTransformInfo.h
index 6895cd0698c65..8c6fb262486f1 100644
--- a/llvm/lib/Target/ARM/ARMTargetTransformInfo.h
+++ b/llvm/lib/Target/ARM/ARMTargetTransformInfo.h
@@ -247,9 +247,9 @@ class ARMTTIImpl : public BasicTTIImplBase<ARMTTIImpl> {
TTI::TargetCostKind CostKind,
const Instruction *I = nullptr);
- int getArithmeticReductionCost(unsigned Opcode, VectorType *ValTy,
- bool IsPairwiseForm,
- TTI::TargetCostKind CostKind);
+ InstructionCost getArithmeticReductionCost(unsigned Opcode, VectorType *ValTy,
+ bool IsPairwiseForm,
+ TTI::TargetCostKind CostKind);
InstructionCost getExtendedAddReductionCost(bool IsMLA, bool IsUnsigned,
Type *ResTy, VectorType *ValTy,
TTI::TargetCostKind CostKind);
diff --git a/llvm/lib/Target/X86/X86TargetTransformInfo.cpp b/llvm/lib/Target/X86/X86TargetTransformInfo.cpp
index 51803798493e4..c63b39ed124bb 100644
--- a/llvm/lib/Target/X86/X86TargetTransformInfo.cpp
+++ b/llvm/lib/Target/X86/X86TargetTransformInfo.cpp
@@ -3340,9 +3340,10 @@ int X86TTIImpl::getAddressComputationCost(Type *Ty, ScalarEvolution *SE,
return BaseT::getAddressComputationCost(Ty, SE, Ptr);
}
-int X86TTIImpl::getArithmeticReductionCost(unsigned Opcode, VectorType *ValTy,
- bool IsPairwise,
- TTI::TargetCostKind CostKind) {
+InstructionCost
+X86TTIImpl::getArithmeticReductionCost(unsigned Opcode, VectorType *ValTy,
+ bool IsPairwise,
+ TTI::TargetCostKind CostKind) {
// Just use the default implementation for pair reductions.
if (IsPairwise)
return BaseT::getArithmeticReductionCost(Opcode, ValTy, IsPairwise, CostKind);
diff --git a/llvm/lib/Target/X86/X86TargetTransformInfo.h b/llvm/lib/Target/X86/X86TargetTransformInfo.h
index 84e459cccc1ca..91a8091935cd9 100644
--- a/llvm/lib/Target/X86/X86TargetTransformInfo.h
+++ b/llvm/lib/Target/X86/X86TargetTransformInfo.h
@@ -175,9 +175,9 @@ class X86TTIImpl : public BasicTTIImplBase<X86TTIImpl> {
InstructionCost getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA,
TTI::TargetCostKind CostKind);
- int getArithmeticReductionCost(unsigned Opcode, VectorType *Ty,
- bool IsPairwiseForm,
- TTI::TargetCostKind CostKind = TTI::TCK_SizeAndLatency);
+ InstructionCost getArithmeticReductionCost(
+ unsigned Opcode, VectorType *Ty, bool IsPairwiseForm,
+ TTI::TargetCostKind CostKind = TTI::TCK_SizeAndLatency);
int getMinMaxCost(Type *Ty, Type *CondTy, bool IsUnsigned);
diff --git a/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp b/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
index 02ccbfc525460..3727be8b02dda 100644
--- a/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
+++ b/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
@@ -6990,8 +6990,8 @@ InstructionCost LoopVectorizationCostModel::getReductionPatternCost(
RecurrenceDescriptor RdxDesc =
Legal->getReductionVars()[cast<PHINode>(ReductionPhi)];
- unsigned BaseCost = TTI.getArithmeticReductionCost(RdxDesc.getOpcode(),
- VectorTy, false, CostKind);
+ InstructionCost BaseCost = TTI.getArithmeticReductionCost(
+ RdxDesc.getOpcode(), VectorTy, false, CostKind);
// Get the operand that was not the reduction chain and match it to one of the
// patterns, returning the better cost if it is found.
diff --git a/llvm/test/Analysis/CostModel/AArch64/sve-intrinsics.ll b/llvm/test/Analysis/CostModel/AArch64/sve-intrinsics.ll
index ee99c579824e1..f0c11e2442036 100644
--- a/llvm/test/Analysis/CostModel/AArch64/sve-intrinsics.ll
+++ b/llvm/test/Analysis/CostModel/AArch64/sve-intrinsics.ll
@@ -22,8 +22,8 @@ define void @reductions(<vscale x 4 x i32> %v0, <vscale x 4 x i64> %v1, <vscale
; CHECK-LABEL: 'reductions'
; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %add_nxv4i32 = call i32 @llvm.vector.reduce.add.nxv4i32(<vscale x 4 x i32> %v0)
; CHECK-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %add_nxv4i64 = call i64 @llvm.vector.reduce.add.nxv4i64(<vscale x 4 x i64> %v1)
-; CHECK-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %mul_nxv4i32 = call i32 @llvm.vector.reduce.mul.nxv4i32(<vscale x 4 x i32> %v0)
-; CHECK-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %mul_nxv4i64 = call i64 @llvm.vector.reduce.mul.nxv4i64(<vscale x 4 x i64> %v1)
+; CHECK-NEXT: Cost Model: Invalid cost for instruction: %mul_nxv4i32 = call i32 @llvm.vector.reduce.mul.nxv4i32(<vscale x 4 x i32> %v0)
+; CHECK-NEXT: Cost Model: Invalid cost for instruction: %mul_nxv4i64 = call i64 @llvm.vector.reduce.mul.nxv4i64(<vscale x 4 x i64> %v1)
; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %and_nxv4i32 = call i32 @llvm.vector.reduce.and.nxv4i32(<vscale x 4 x i32> %v0)
; CHECK-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %and_nxv4i64 = call i64 @llvm.vector.reduce.and.nxv4i64(<vscale x 4 x i64> %v1)
; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %or_nxv4i32 = call i32 @llvm.vector.reduce.or.nxv4i32(<vscale x 4 x i32> %v0)
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