[PATCH] D99272: [AArch64] Adds a pre-indexed paired Load/Store optimization for LDR-STR.

[Stelios Ioannou via Phabricator via llvm-commits]

stelios-arm updated this revision to Diff 337087.
stelios-arm added a comment.

Removed the hack that was used to avoid the `memoperands_empty()` check for `LDR<>pre` instructions.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D99272/new/

https://reviews.llvm.org/D99272

Files:
  llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
  llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp
  llvm/test/CodeGen/AArch64/arm64-memset-inline.ll
  llvm/test/CodeGen/AArch64/ldrpre-ldr-merge.mir
  llvm/test/CodeGen/AArch64/strpre-str-merge.mir

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