[PATCH] D99662: [AArch64] Add Machine InstCombiner patterns for FMUL indexed variant

[Andrew Savonichev via Phabricator via llvm-commits]

asavonic updated this revision to Diff 336950.
asavonic added a comment.

There were two issues with the patch, so I reverted it:

1. The register operand of VDUP was used for VMUL_indexed. This does not work correctly if the register has a killed state.

2. VMUL_indexed requires the second operand to have FPR128_lo register class instead of FPR128.

I've fixed this by adding a COPY instruction before the VDUP, but I'm not sure if it is legal to do so in `genAlternativeCodeSequence` function. If I understand correctly, `genAlternativeCodeSequence` is supposed to add new instructions to the `InsInstrs`, not modify the MIR function directly. On the other hand, I assume that the COPY will be removed if Machine InstCombiner decides the discard the result.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D99662/new/

https://reviews.llvm.org/D99662

Files:
  llvm/include/llvm/CodeGen/MachineCombinerPattern.h
  llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
  llvm/test/CodeGen/AArch64/arm64-fma-combines.ll
  llvm/test/CodeGen/AArch64/machine-combiner-fmul-dup.mir

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