[llvm] cfce5b2 - [ARM] support symbolic expression as immediate in memory instructions
Jian Cai via llvm-commits
llvm-commits at lists.llvm.org
Mon Apr 12 12:14:02 PDT 2021
Author: Jian Cai
Date: 2021-04-12T12:13:55-07:00
New Revision: cfce5b26a888cb979d65252275df1f977dc1e6c8
URL: https://github.com/llvm/llvm-project/commit/cfce5b26a888cb979d65252275df1f977dc1e6c8
DIFF: https://github.com/llvm/llvm-project/commit/cfce5b26a888cb979d65252275df1f977dc1e6c8.diff
LOG: [ARM] support symbolic expression as immediate in memory instructions
Currently the ARM backend only accpets constant expressions as the
immediate operand in load and store instructions. This allows the
result of symbolic expressions to be used in memory instructions. For
example,
0:
.space 2048
strb r2, [r0, #(.-0b)]
would be assembled into the following instructions.
strb r2, [r0, #2048]
This only adds support to ldr, ldrb, str, and strb in arm mode to
address the build failure of Linux kernel for now, but should facilitate
adding support to similar instructions in the future if the need arises.
Link:
https://github.com/ClangBuiltLinux/linux/issues/1329
Reviewed By: peter.smith, nickdesaulniers
Differential Revision: https://reviews.llvm.org/D98916
Added:
llvm/test/MC/ARM/arm-memory-instructions-immediate.s
Modified:
llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp
llvm/lib/Target/ARM/MCTargetDesc/ARMFixupKinds.h
llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
Removed:
################################################################################
diff --git a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
index 9a2d94e3972c2..a3724f3352616 100644
--- a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
+++ b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
@@ -847,7 +847,7 @@ class ARMOperand : public MCParsedAsmOperand {
unsigned BaseRegNum;
// Offset is in OffsetReg or OffsetImm. If both are zero, no offset
// was specified.
- const MCConstantExpr *OffsetImm; // Offset immediate value
+ const MCExpr *OffsetImm; // Offset immediate value
unsigned OffsetRegNum; // Offset register num, when OffsetImm == NULL
ARM_AM::ShiftOpc ShiftType; // Shift type for OffsetReg
unsigned ShiftImm; // shift for OffsetReg.
@@ -1107,7 +1107,10 @@ class ARMOperand : public MCParsedAsmOperand {
else if (isGPRMem()) {
if(!Memory.OffsetImm || Memory.OffsetRegNum) return false;
if(Memory.BaseRegNum != ARM::PC) return false;
- Val = Memory.OffsetImm->getValue();
+ if (const auto *CE = dyn_cast<MCConstantExpr>(Memory.OffsetImm))
+ Val = CE->getValue();
+ else
+ return false;
}
else return false;
return ((Val % 4) == 0) && (Val >= 0) && (Val <= 1020);
@@ -1496,9 +1499,12 @@ class ARMOperand : public MCParsedAsmOperand {
return false;
// Immediate offset in range [-4095, 4095].
if (!Memory.OffsetImm) return true;
- int64_t Val = Memory.OffsetImm->getValue();
- return (Val > -4096 && Val < 4096) ||
- (Val == std::numeric_limits<int32_t>::min());
+ if (const auto *CE = dyn_cast<MCConstantExpr>(Memory.OffsetImm)) {
+ int64_t Val = CE->getValue();
+ return (Val > -4096 && Val < 4096) ||
+ (Val == std::numeric_limits<int32_t>::min());
+ }
+ return false;
}
bool isAlignedMemory() const {
@@ -1581,8 +1587,11 @@ class ARMOperand : public MCParsedAsmOperand {
if (Memory.OffsetRegNum) return true;
// Immediate offset in range [-4095, 4095].
if (!Memory.OffsetImm) return true;
- int64_t Val = Memory.OffsetImm->getValue();
- return Val > -4096 && Val < 4096;
+ if (const auto *CE = dyn_cast<MCConstantExpr>(Memory.OffsetImm)) {
+ int64_t Val = CE->getValue();
+ return Val > -4096 && Val < 4096;
+ }
+ return false;
}
bool isAM2OffsetImm() const {
@@ -1608,11 +1617,14 @@ class ARMOperand : public MCParsedAsmOperand {
if (Memory.OffsetRegNum) return true;
// Immediate offset in range [-255, 255].
if (!Memory.OffsetImm) return true;
- int64_t Val = Memory.OffsetImm->getValue();
- // The #-0 offset is encoded as std::numeric_limits<int32_t>::min(), and we
- // have to check for this too.
- return (Val > -256 && Val < 256) ||
- Val == std::numeric_limits<int32_t>::min();
+ if (const auto *CE = dyn_cast<MCConstantExpr>(Memory.OffsetImm)) {
+ int64_t Val = CE->getValue();
+ // The #-0 offset is encoded as std::numeric_limits<int32_t>::min(), and
+ // we have to check for this too.
+ return (Val > -256 && Val < 256) ||
+ Val == std::numeric_limits<int32_t>::min();
+ }
+ return false;
}
bool isAM3Offset() const {
@@ -1640,9 +1652,12 @@ class ARMOperand : public MCParsedAsmOperand {
if (Memory.OffsetRegNum) return false;
// Immediate offset in range [-1020, 1020] and a multiple of 4.
if (!Memory.OffsetImm) return true;
- int64_t Val = Memory.OffsetImm->getValue();
- return (Val >= -1020 && Val <= 1020 && ((Val & 3) == 0)) ||
- Val == std::numeric_limits<int32_t>::min();
+ if (const auto *CE = dyn_cast<MCConstantExpr>(Memory.OffsetImm)) {
+ int64_t Val = CE->getValue();
+ return (Val >= -1020 && Val <= 1020 && ((Val & 3) == 0)) ||
+ Val == std::numeric_limits<int32_t>::min();
+ }
+ return false;
}
bool isAddrMode5FP16() const {
@@ -1656,9 +1671,12 @@ class ARMOperand : public MCParsedAsmOperand {
if (Memory.OffsetRegNum) return false;
// Immediate offset in range [-510, 510] and a multiple of 2.
if (!Memory.OffsetImm) return true;
- int64_t Val = Memory.OffsetImm->getValue();
- return (Val >= -510 && Val <= 510 && ((Val & 1) == 0)) ||
- Val == std::numeric_limits<int32_t>::min();
+ if (const auto *CE = dyn_cast<MCConstantExpr>(Memory.OffsetImm)) {
+ int64_t Val = CE->getValue();
+ return (Val >= -510 && Val <= 510 && ((Val & 1) == 0)) ||
+ Val == std::numeric_limits<int32_t>::min();
+ }
+ return false;
}
bool isMemTBB() const {
@@ -1710,8 +1728,11 @@ class ARMOperand : public MCParsedAsmOperand {
return false;
// Immediate offset, multiple of 4 in range [0, 124].
if (!Memory.OffsetImm) return true;
- int64_t Val = Memory.OffsetImm->getValue();
- return Val >= 0 && Val <= 124 && (Val % 4) == 0;
+ if (const auto *CE = dyn_cast<MCConstantExpr>(Memory.OffsetImm)) {
+ int64_t Val = CE->getValue();
+ return Val >= 0 && Val <= 124 && (Val % 4) == 0;
+ }
+ return false;
}
bool isMemThumbRIs2() const {
@@ -1720,8 +1741,11 @@ class ARMOperand : public MCParsedAsmOperand {
return false;
// Immediate offset, multiple of 4 in range [0, 62].
if (!Memory.OffsetImm) return true;
- int64_t Val = Memory.OffsetImm->getValue();
- return Val >= 0 && Val <= 62 && (Val % 2) == 0;
+ if (const auto *CE = dyn_cast<MCConstantExpr>(Memory.OffsetImm)) {
+ int64_t Val = CE->getValue();
+ return Val >= 0 && Val <= 62 && (Val % 2) == 0;
+ }
+ return false;
}
bool isMemThumbRIs1() const {
@@ -1730,8 +1754,11 @@ class ARMOperand : public MCParsedAsmOperand {
return false;
// Immediate offset in range [0, 31].
if (!Memory.OffsetImm) return true;
- int64_t Val = Memory.OffsetImm->getValue();
- return Val >= 0 && Val <= 31;
+ if (const auto *CE = dyn_cast<MCConstantExpr>(Memory.OffsetImm)) {
+ int64_t Val = CE->getValue();
+ return Val >= 0 && Val <= 31;
+ }
+ return false;
}
bool isMemThumbSPI() const {
@@ -1740,8 +1767,11 @@ class ARMOperand : public MCParsedAsmOperand {
return false;
// Immediate offset, multiple of 4 in range [0, 1020].
if (!Memory.OffsetImm) return true;
- int64_t Val = Memory.OffsetImm->getValue();
- return Val >= 0 && Val <= 1020 && (Val % 4) == 0;
+ if (const auto *CE = dyn_cast<MCConstantExpr>(Memory.OffsetImm)) {
+ int64_t Val = CE->getValue();
+ return Val >= 0 && Val <= 1020 && (Val % 4) == 0;
+ }
+ return false;
}
bool isMemImm8s4Offset() const {
@@ -1754,11 +1784,15 @@ class ARMOperand : public MCParsedAsmOperand {
return false;
// Immediate offset a multiple of 4 in range [-1020, 1020].
if (!Memory.OffsetImm) return true;
- int64_t Val = Memory.OffsetImm->getValue();
- // Special case, #-0 is std::numeric_limits<int32_t>::min().
- return (Val >= -1020 && Val <= 1020 && (Val & 3) == 0) ||
- Val == std::numeric_limits<int32_t>::min();
+ if (const auto *CE = dyn_cast<MCConstantExpr>(Memory.OffsetImm)) {
+ int64_t Val = CE->getValue();
+ // Special case, #-0 is std::numeric_limits<int32_t>::min().
+ return (Val >= -1020 && Val <= 1020 && (Val & 3) == 0) ||
+ Val == std::numeric_limits<int32_t>::min();
+ }
+ return false;
}
+
bool isMemImm7s4Offset() const {
// If we have an immediate that's not a constant, treat it as a label
// reference needing a fixup. If it is a constant, it's something else
@@ -1771,17 +1805,24 @@ class ARMOperand : public MCParsedAsmOperand {
return false;
// Immediate offset a multiple of 4 in range [-508, 508].
if (!Memory.OffsetImm) return true;
- int64_t Val = Memory.OffsetImm->getValue();
- // Special case, #-0 is INT32_MIN.
- return (Val >= -508 && Val <= 508 && (Val & 3) == 0) || Val == INT32_MIN;
+ if (const auto *CE = dyn_cast<MCConstantExpr>(Memory.OffsetImm)) {
+ int64_t Val = CE->getValue();
+ // Special case, #-0 is INT32_MIN.
+ return (Val >= -508 && Val <= 508 && (Val & 3) == 0) || Val == INT32_MIN;
+ }
+ return false;
}
+
bool isMemImm0_1020s4Offset() const {
if (!isGPRMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
return false;
// Immediate offset a multiple of 4 in range [0, 1020].
if (!Memory.OffsetImm) return true;
- int64_t Val = Memory.OffsetImm->getValue();
- return Val >= 0 && Val <= 1020 && (Val & 3) == 0;
+ if (const auto *CE = dyn_cast<MCConstantExpr>(Memory.OffsetImm)) {
+ int64_t Val = CE->getValue();
+ return Val >= 0 && Val <= 1020 && (Val & 3) == 0;
+ }
+ return false;
}
bool isMemImm8Offset() const {
@@ -1791,9 +1832,12 @@ class ARMOperand : public MCParsedAsmOperand {
if (Memory.BaseRegNum == ARM::PC) return false;
// Immediate offset in range [-255, 255].
if (!Memory.OffsetImm) return true;
- int64_t Val = Memory.OffsetImm->getValue();
- return (Val == std::numeric_limits<int32_t>::min()) ||
- (Val > -256 && Val < 256);
+ if (const auto *CE = dyn_cast<MCConstantExpr>(Memory.OffsetImm)) {
+ int64_t Val = CE->getValue();
+ return (Val == std::numeric_limits<int32_t>::min()) ||
+ (Val > -256 && Val < 256);
+ }
+ return false;
}
template<unsigned Bits, unsigned RegClassID>
@@ -1806,22 +1850,25 @@ class ARMOperand : public MCParsedAsmOperand {
// [-127, 127], shifted left by Bits.
if (!Memory.OffsetImm) return true;
- int64_t Val = Memory.OffsetImm->getValue();
+ if (const auto *CE = dyn_cast<MCConstantExpr>(Memory.OffsetImm)) {
+ int64_t Val = CE->getValue();
- // INT32_MIN is a special-case value (indicating the encoding with
- // zero offset and the subtract bit set)
- if (Val == INT32_MIN)
- return true;
+ // INT32_MIN is a special-case value (indicating the encoding with
+ // zero offset and the subtract bit set)
+ if (Val == INT32_MIN)
+ return true;
- unsigned Divisor = 1U << Bits;
+ unsigned Divisor = 1U << Bits;
- // Check that the low bits are zero
- if (Val % Divisor != 0)
- return false;
+ // Check that the low bits are zero
+ if (Val % Divisor != 0)
+ return false;
- // Check that the remaining offset is within range.
- Val /= Divisor;
- return (Val >= -127 && Val <= 127);
+ // Check that the remaining offset is within range.
+ Val /= Divisor;
+ return (Val >= -127 && Val <= 127);
+ }
+ return false;
}
template <int shift> bool isMemRegRQOffset() const {
@@ -1853,20 +1900,24 @@ class ARMOperand : public MCParsedAsmOperand {
Memory.BaseRegNum))
return false;
- if(!Memory.OffsetImm) return true;
+ if (!Memory.OffsetImm)
+ return true;
static_assert(shift < 56,
"Such that we dont shift by a value higher than 62");
- int64_t Val = Memory.OffsetImm->getValue();
+ if (const auto *CE = dyn_cast<MCConstantExpr>(Memory.OffsetImm)) {
+ int64_t Val = CE->getValue();
- // The value must be a multiple of (1 << shift)
- if ((Val & ((1U << shift) - 1)) != 0)
- return false;
+ // The value must be a multiple of (1 << shift)
+ if ((Val & ((1U << shift) - 1)) != 0)
+ return false;
- // And be in the right range, depending on the amount that it is shifted
- // by. Shift 0, is equal to 7 unsigned bits, the sign bit is set
- // separately.
- int64_t Range = (1U << (7+shift)) - 1;
- return (Val == INT32_MIN) || (Val > -Range && Val < Range);
+ // And be in the right range, depending on the amount that it is shifted
+ // by. Shift 0, is equal to 7 unsigned bits, the sign bit is set
+ // separately.
+ int64_t Range = (1U << (7 + shift)) - 1;
+ return (Val == INT32_MIN) || (Val > -Range && Val < Range);
+ }
+ return false;
}
bool isMemPosImm8Offset() const {
@@ -1874,8 +1925,11 @@ class ARMOperand : public MCParsedAsmOperand {
return false;
// Immediate offset in range [0, 255].
if (!Memory.OffsetImm) return true;
- int64_t Val = Memory.OffsetImm->getValue();
- return Val >= 0 && Val < 256;
+ if (const auto *CE = dyn_cast<MCConstantExpr>(Memory.OffsetImm)) {
+ int64_t Val = CE->getValue();
+ return Val >= 0 && Val < 256;
+ }
+ return false;
}
bool isMemNegImm8Offset() const {
@@ -1885,9 +1939,12 @@ class ARMOperand : public MCParsedAsmOperand {
if (Memory.BaseRegNum == ARM::PC) return false;
// Immediate offset in range [-255, -1].
if (!Memory.OffsetImm) return false;
- int64_t Val = Memory.OffsetImm->getValue();
- return (Val == std::numeric_limits<int32_t>::min()) ||
- (Val > -256 && Val < 0);
+ if (const auto *CE = dyn_cast<MCConstantExpr>(Memory.OffsetImm)) {
+ int64_t Val = CE->getValue();
+ return (Val == std::numeric_limits<int32_t>::min()) ||
+ (Val > -256 && Val < 0);
+ }
+ return false;
}
bool isMemUImm12Offset() const {
@@ -1895,8 +1952,11 @@ class ARMOperand : public MCParsedAsmOperand {
return false;
// Immediate offset in range [0, 4095].
if (!Memory.OffsetImm) return true;
- int64_t Val = Memory.OffsetImm->getValue();
- return (Val >= 0 && Val < 4096);
+ if (const auto *CE = dyn_cast<MCConstantExpr>(Memory.OffsetImm)) {
+ int64_t Val = CE->getValue();
+ return (Val >= 0 && Val < 4096);
+ }
+ return false;
}
bool isMemImm12Offset() const {
@@ -1911,9 +1971,14 @@ class ARMOperand : public MCParsedAsmOperand {
return false;
// Immediate offset in range [-4095, 4095].
if (!Memory.OffsetImm) return true;
- int64_t Val = Memory.OffsetImm->getValue();
- return (Val > -4096 && Val < 4096) ||
- (Val == std::numeric_limits<int32_t>::min());
+ if (const auto *CE = dyn_cast<MCConstantExpr>(Memory.OffsetImm)) {
+ int64_t Val = CE->getValue();
+ return (Val > -4096 && Val < 4096) ||
+ (Val == std::numeric_limits<int32_t>::min());
+ }
+ // If we have an immediate that's not a constant, treat it as a
+ // symbolic expression needing a fixup.
+ return true;
}
bool isConstPoolAsmImm() const {
@@ -2760,7 +2825,10 @@ class ARMOperand : public MCParsedAsmOperand {
assert(isGPRMem() && "Unknown value type!");
assert(isa<MCConstantExpr>(Memory.OffsetImm) && "Unknown value type!");
- Inst.addOperand(MCOperand::createImm(Memory.OffsetImm->getValue()));
+ if (const auto *CE = dyn_cast<MCConstantExpr>(Memory.OffsetImm))
+ Inst.addOperand(MCOperand::createImm(CE->getValue()));
+ else
+ Inst.addOperand(MCOperand::createExpr(Memory.OffsetImm));
}
void addMemBarrierOptOperands(MCInst &Inst, unsigned N) const {
@@ -2800,8 +2868,10 @@ class ARMOperand : public MCParsedAsmOperand {
void addMemPCRelImm12Operands(MCInst &Inst, unsigned N) const {
assert(N == 1 && "Invalid number of operands!");
- int32_t Imm = Memory.OffsetImm->getValue();
- Inst.addOperand(MCOperand::createImm(Imm));
+ if (const auto *CE = dyn_cast<MCConstantExpr>(Memory.OffsetImm))
+ Inst.addOperand(MCOperand::createImm(CE->getValue()));
+ else
+ Inst.addOperand(MCOperand::createExpr(Memory.OffsetImm));
}
void addAdrLabelOperands(MCInst &Inst, unsigned N) const {
@@ -2872,22 +2942,31 @@ class ARMOperand : public MCParsedAsmOperand {
void addAddrMode2Operands(MCInst &Inst, unsigned N) const {
assert(N == 3 && "Invalid number of operands!");
- int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
+ Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
+ Inst.addOperand(MCOperand::createReg(Memory.OffsetRegNum));
if (!Memory.OffsetRegNum) {
- ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
- // Special case for #-0
- if (Val == std::numeric_limits<int32_t>::min()) Val = 0;
- if (Val < 0) Val = -Val;
- Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift);
+ if (!Memory.OffsetImm)
+ Inst.addOperand(MCOperand::createImm(0));
+ else if (const auto *CE = dyn_cast<MCConstantExpr>(Memory.OffsetImm)) {
+ int32_t Val = CE->getValue();
+ ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
+ // Special case for #-0
+ if (Val == std::numeric_limits<int32_t>::min())
+ Val = 0;
+ if (Val < 0)
+ Val = -Val;
+ Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift);
+ Inst.addOperand(MCOperand::createImm(Val));
+ } else
+ Inst.addOperand(MCOperand::createExpr(Memory.OffsetImm));
} else {
// For register offset, we encode the shift type and negation flag
// here.
- Val = ARM_AM::getAM2Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add,
- Memory.ShiftImm, Memory.ShiftType);
+ int32_t Val =
+ ARM_AM::getAM2Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add,
+ Memory.ShiftImm, Memory.ShiftType);
+ Inst.addOperand(MCOperand::createImm(Val));
}
- Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
- Inst.addOperand(MCOperand::createReg(Memory.OffsetRegNum));
- Inst.addOperand(MCOperand::createImm(Val));
}
void addAM2OffsetImmOperands(MCInst &Inst, unsigned N) const {
@@ -2916,21 +2995,30 @@ class ARMOperand : public MCParsedAsmOperand {
return;
}
- int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
+ Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
+ Inst.addOperand(MCOperand::createReg(Memory.OffsetRegNum));
if (!Memory.OffsetRegNum) {
- ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
- // Special case for #-0
- if (Val == std::numeric_limits<int32_t>::min()) Val = 0;
- if (Val < 0) Val = -Val;
- Val = ARM_AM::getAM3Opc(AddSub, Val);
+ if (!Memory.OffsetImm)
+ Inst.addOperand(MCOperand::createImm(0));
+ else if (const auto *CE = dyn_cast<MCConstantExpr>(Memory.OffsetImm)) {
+ int32_t Val = CE->getValue();
+ ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
+ // Special case for #-0
+ if (Val == std::numeric_limits<int32_t>::min())
+ Val = 0;
+ if (Val < 0)
+ Val = -Val;
+ Val = ARM_AM::getAM3Opc(AddSub, Val);
+ Inst.addOperand(MCOperand::createImm(Val));
+ } else
+ Inst.addOperand(MCOperand::createExpr(Memory.OffsetImm));
} else {
// For register offset, we encode the shift type and negation flag
// here.
- Val = ARM_AM::getAM3Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add, 0);
+ int32_t Val =
+ ARM_AM::getAM3Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add, 0);
+ Inst.addOperand(MCOperand::createImm(Val));
}
- Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
- Inst.addOperand(MCOperand::createReg(Memory.OffsetRegNum));
- Inst.addOperand(MCOperand::createImm(Val));
}
void addAM3OffsetOperands(MCInst &Inst, unsigned N) const {
@@ -2966,15 +3054,22 @@ class ARMOperand : public MCParsedAsmOperand {
return;
}
- // The lower two bits are always zero and as such are not encoded.
- int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() / 4 : 0;
- ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
- // Special case for #-0
- if (Val == std::numeric_limits<int32_t>::min()) Val = 0;
- if (Val < 0) Val = -Val;
- Val = ARM_AM::getAM5Opc(AddSub, Val);
Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
- Inst.addOperand(MCOperand::createImm(Val));
+ if (!Memory.OffsetImm)
+ Inst.addOperand(MCOperand::createImm(0));
+ else if (const auto *CE = dyn_cast<MCConstantExpr>(Memory.OffsetImm)) {
+ // The lower two bits are always zero and as such are not encoded.
+ int32_t Val = CE->getValue() / 4;
+ ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
+ // Special case for #-0
+ if (Val == std::numeric_limits<int32_t>::min())
+ Val = 0;
+ if (Val < 0)
+ Val = -Val;
+ Val = ARM_AM::getAM5Opc(AddSub, Val);
+ Inst.addOperand(MCOperand::createImm(Val));
+ } else
+ Inst.addOperand(MCOperand::createExpr(Memory.OffsetImm));
}
void addAddrMode5FP16Operands(MCInst &Inst, unsigned N) const {
@@ -2988,15 +3083,22 @@ class ARMOperand : public MCParsedAsmOperand {
return;
}
- // The lower bit is always zero and as such is not encoded.
- int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() / 2 : 0;
- ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
- // Special case for #-0
- if (Val == std::numeric_limits<int32_t>::min()) Val = 0;
- if (Val < 0) Val = -Val;
- Val = ARM_AM::getAM5FP16Opc(AddSub, Val);
Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
- Inst.addOperand(MCOperand::createImm(Val));
+ // The lower bit is always zero and as such is not encoded.
+ if (!Memory.OffsetImm)
+ Inst.addOperand(MCOperand::createImm(0));
+ else if (const auto *CE = dyn_cast<MCConstantExpr>(Memory.OffsetImm)) {
+ int32_t Val = CE->getValue() / 2;
+ ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
+ // Special case for #-0
+ if (Val == std::numeric_limits<int32_t>::min())
+ Val = 0;
+ if (Val < 0)
+ Val = -Val;
+ Val = ARM_AM::getAM5FP16Opc(AddSub, Val);
+ Inst.addOperand(MCOperand::createImm(Val));
+ } else
+ Inst.addOperand(MCOperand::createExpr(Memory.OffsetImm));
}
void addMemImm8s4OffsetOperands(MCInst &Inst, unsigned N) const {
@@ -3010,9 +3112,8 @@ class ARMOperand : public MCParsedAsmOperand {
return;
}
- int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
- Inst.addOperand(MCOperand::createImm(Val));
+ addExpr(Inst, Memory.OffsetImm);
}
void addMemImm7s4OffsetOperands(MCInst &Inst, unsigned N) const {
@@ -3026,24 +3127,26 @@ class ARMOperand : public MCParsedAsmOperand {
return;
}
- int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
- Inst.addOperand(MCOperand::createImm(Val));
+ addExpr(Inst, Memory.OffsetImm);
}
void addMemImm0_1020s4OffsetOperands(MCInst &Inst, unsigned N) const {
assert(N == 2 && "Invalid number of operands!");
- // The lower two bits are always zero and as such are not encoded.
- int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() / 4 : 0;
Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
- Inst.addOperand(MCOperand::createImm(Val));
+ if (!Memory.OffsetImm)
+ Inst.addOperand(MCOperand::createImm(0));
+ else if (const auto *CE = dyn_cast<MCConstantExpr>(Memory.OffsetImm))
+ // The lower two bits are always zero and as such are not encoded.
+ Inst.addOperand(MCOperand::createImm(CE->getValue() / 4));
+ else
+ Inst.addOperand(MCOperand::createExpr(Memory.OffsetImm));
}
void addMemImmOffsetOperands(MCInst &Inst, unsigned N) const {
assert(N == 2 && "Invalid number of operands!");
- int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
- Inst.addOperand(MCOperand::createImm(Val));
+ addExpr(Inst, Memory.OffsetImm);
}
void addMemRegRQOffsetOperands(MCInst &Inst, unsigned N) const {
@@ -3062,9 +3165,8 @@ class ARMOperand : public MCParsedAsmOperand {
}
// Otherwise, it's a normal memory reg+offset.
- int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
- Inst.addOperand(MCOperand::createImm(Val));
+ addExpr(Inst, Memory.OffsetImm);
}
void addMemImm12OffsetOperands(MCInst &Inst, unsigned N) const {
@@ -3077,9 +3179,8 @@ class ARMOperand : public MCParsedAsmOperand {
}
// Otherwise, it's a normal memory reg+offset.
- int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
- Inst.addOperand(MCOperand::createImm(Val));
+ addExpr(Inst, Memory.OffsetImm);
}
void addConstPoolAsmImmOperands(MCInst &Inst, unsigned N) const {
@@ -3126,30 +3227,43 @@ class ARMOperand : public MCParsedAsmOperand {
void addMemThumbRIs4Operands(MCInst &Inst, unsigned N) const {
assert(N == 2 && "Invalid number of operands!");
- int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 4) : 0;
Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
- Inst.addOperand(MCOperand::createImm(Val));
+ if (!Memory.OffsetImm)
+ Inst.addOperand(MCOperand::createImm(0));
+ else if (const auto *CE = dyn_cast<MCConstantExpr>(Memory.OffsetImm))
+ // The lower two bits are always zero and as such are not encoded.
+ Inst.addOperand(MCOperand::createImm(CE->getValue() / 4));
+ else
+ Inst.addOperand(MCOperand::createExpr(Memory.OffsetImm));
}
void addMemThumbRIs2Operands(MCInst &Inst, unsigned N) const {
assert(N == 2 && "Invalid number of operands!");
- int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 2) : 0;
Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
- Inst.addOperand(MCOperand::createImm(Val));
+ if (!Memory.OffsetImm)
+ Inst.addOperand(MCOperand::createImm(0));
+ else if (const auto *CE = dyn_cast<MCConstantExpr>(Memory.OffsetImm))
+ Inst.addOperand(MCOperand::createImm(CE->getValue() / 2));
+ else
+ Inst.addOperand(MCOperand::createExpr(Memory.OffsetImm));
}
void addMemThumbRIs1Operands(MCInst &Inst, unsigned N) const {
assert(N == 2 && "Invalid number of operands!");
- int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue()) : 0;
Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
- Inst.addOperand(MCOperand::createImm(Val));
+ addExpr(Inst, Memory.OffsetImm);
}
void addMemThumbSPIOperands(MCInst &Inst, unsigned N) const {
assert(N == 2 && "Invalid number of operands!");
- int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 4) : 0;
Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
- Inst.addOperand(MCOperand::createImm(Val));
+ if (!Memory.OffsetImm)
+ Inst.addOperand(MCOperand::createImm(0));
+ else if (const auto *CE = dyn_cast<MCConstantExpr>(Memory.OffsetImm))
+ // The lower two bits are always zero and as such are not encoded.
+ Inst.addOperand(MCOperand::createImm(CE->getValue() / 4));
+ else
+ Inst.addOperand(MCOperand::createExpr(Memory.OffsetImm));
}
void addPostIdxImm8Operands(MCInst &Inst, unsigned N) const {
@@ -3686,10 +3800,9 @@ class ARMOperand : public MCParsedAsmOperand {
}
static std::unique_ptr<ARMOperand>
- CreateMem(unsigned BaseRegNum, const MCConstantExpr *OffsetImm,
- unsigned OffsetRegNum, ARM_AM::ShiftOpc ShiftType,
- unsigned ShiftImm, unsigned Alignment, bool isNegative, SMLoc S,
- SMLoc E, SMLoc AlignmentLoc = SMLoc()) {
+ CreateMem(unsigned BaseRegNum, const MCExpr *OffsetImm, unsigned OffsetRegNum,
+ ARM_AM::ShiftOpc ShiftType, unsigned ShiftImm, unsigned Alignment,
+ bool isNegative, SMLoc S, SMLoc E, SMLoc AlignmentLoc = SMLoc()) {
auto Op = std::make_unique<ARMOperand>(k_Memory);
Op->Memory.BaseRegNum = BaseRegNum;
Op->Memory.OffsetImm = OffsetImm;
@@ -5818,23 +5931,24 @@ bool ARMAsmParser::parseMemory(OperandVector &Operands) {
E = Parser.getTok().getLoc();
bool isNegative = getParser().getTok().is(AsmToken::Minus);
- const MCExpr *Offset;
+ const MCExpr *Offset, *AdjustedOffset;
if (getParser().parseExpression(Offset))
return true;
- // The expression has to be a constant. Memory references with relocations
- // don't come through here, as they use the <label> forms of the relevant
- // instructions.
- const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset);
- if (!CE)
- return Error (E, "constant expression expected");
-
- // If the constant was #-0, represent it as
- // std::numeric_limits<int32_t>::min().
- int32_t Val = CE->getValue();
- if (isNegative && Val == 0)
- CE = MCConstantExpr::create(std::numeric_limits<int32_t>::min(),
- getContext());
+ if (const auto *CE = dyn_cast<MCConstantExpr>(Offset)) {
+ // If the constant was #-0, represent it as
+ // std::numeric_limits<int32_t>::min().
+ int32_t Val = CE->getValue();
+ if (isNegative && Val == 0)
+ CE = MCConstantExpr::create(std::numeric_limits<int32_t>::min(),
+ getContext());
+ // Don't worry about range checking the value here. That's handled by
+ // the is*() predicates.
+ AdjustedOffset = CE;
+ } else
+ AdjustedOffset = Offset;
+ Operands.push_back(ARMOperand::CreateMem(
+ BaseRegNum, AdjustedOffset, 0, ARM_AM::no_shift, 0, 0, false, S, E));
// Now we should have the closing ']'
if (Parser.getTok().isNot(AsmToken::RBrac))
@@ -5842,12 +5956,6 @@ bool ARMAsmParser::parseMemory(OperandVector &Operands) {
E = Parser.getTok().getEndLoc();
Parser.Lex(); // Eat right bracket token.
- // Don't worry about range checking the value here. That's handled by
- // the is*() predicates.
- Operands.push_back(ARMOperand::CreateMem(BaseRegNum, CE, 0,
- ARM_AM::no_shift, 0, 0,
- false, S, E));
-
// If there's a pre-indexing writeback marker, '!', just add it as a token
// operand.
if (Parser.getTok().is(AsmToken::Exclaim)) {
diff --git a/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp b/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp
index e272adc7435ee..ea0292253892c 100644
--- a/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp
+++ b/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp
@@ -84,6 +84,7 @@ const MCFixupKindInfo &ARMAsmBackend::getFixupKindInfo(MCFixupKind Kind) const {
{"fixup_arm_pcrel_9", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
{"fixup_t2_pcrel_9", 0, 32,
IsPCRelConstant | MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
+ {"fixup_arm_ldst_abs_12", 0, 32},
{"fixup_thumb_adr_pcrel_10", 0, 8,
IsPCRelConstant | MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
{"fixup_arm_adr_pcrel_12", 0, 32, IsPCRelConstant},
@@ -120,8 +121,7 @@ const MCFixupKindInfo &ARMAsmBackend::getFixupKindInfo(MCFixupKind Kind) const {
{"fixup_bfc_target", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
{"fixup_bfcsel_else_target", 0, 32, 0},
{"fixup_wls", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
- {"fixup_le", 0, 32, MCFixupKindInfo::FKF_IsPCRel}
- };
+ {"fixup_le", 0, 32, MCFixupKindInfo::FKF_IsPCRel}};
const static MCFixupKindInfo InfosBE[ARM::NumTargetFixupKinds] = {
// This table *must* be in the order that the fixup_* kinds are defined in
// ARMFixupKinds.h.
@@ -138,6 +138,7 @@ const MCFixupKindInfo &ARMAsmBackend::getFixupKindInfo(MCFixupKind Kind) const {
{"fixup_arm_pcrel_9", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
{"fixup_t2_pcrel_9", 0, 32,
IsPCRelConstant | MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
+ {"fixup_arm_ldst_abs_12", 0, 32},
{"fixup_thumb_adr_pcrel_10", 8, 8,
IsPCRelConstant | MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
{"fixup_arm_adr_pcrel_12", 0, 32, IsPCRelConstant},
@@ -174,8 +175,7 @@ const MCFixupKindInfo &ARMAsmBackend::getFixupKindInfo(MCFixupKind Kind) const {
{"fixup_bfc_target", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
{"fixup_bfcsel_else_target", 0, 32, 0},
{"fixup_wls", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
- {"fixup_le", 0, 32, MCFixupKindInfo::FKF_IsPCRel}
- };
+ {"fixup_le", 0, 32, MCFixupKindInfo::FKF_IsPCRel}};
// Fixup kinds from .reloc directive are like R_ARM_NONE. They do not require
// any extra processing.
@@ -490,9 +490,11 @@ unsigned ARMAsmBackend::adjustFixupValue(const MCAssembler &Asm,
// ARM PC-relative values are offset by 8.
Value -= 4;
LLVM_FALLTHROUGH;
- case ARM::fixup_t2_ldst_pcrel_12: {
+ case ARM::fixup_t2_ldst_pcrel_12:
// Offset by 4, adjusted by two due to the half-word ordering of thumb.
Value -= 4;
+ LLVM_FALLTHROUGH;
+ case ARM::fixup_arm_ldst_abs_12: {
bool isAdd = true;
if ((int64_t)Value < 0) {
Value = -Value;
@@ -940,6 +942,7 @@ static unsigned getFixupKindNumBytes(unsigned Kind) {
case ARM::fixup_arm_ldst_pcrel_12:
case ARM::fixup_arm_pcrel_10:
case ARM::fixup_arm_pcrel_9:
+ case ARM::fixup_arm_ldst_abs_12:
case ARM::fixup_arm_adr_pcrel_12:
case ARM::fixup_arm_uncondbl:
case ARM::fixup_arm_condbl:
diff --git a/llvm/lib/Target/ARM/MCTargetDesc/ARMFixupKinds.h b/llvm/lib/Target/ARM/MCTargetDesc/ARMFixupKinds.h
index bdf04a208b243..53258a88c7fa2 100644
--- a/llvm/lib/Target/ARM/MCTargetDesc/ARMFixupKinds.h
+++ b/llvm/lib/Target/ARM/MCTargetDesc/ARMFixupKinds.h
@@ -36,6 +36,8 @@ enum Fixups {
// Equivalent to fixup_arm_pcrel_9, accounting for the short-swapped encoding
// of Thumb2 instructions.
fixup_t2_pcrel_9,
+ // 12-bit immediate value.
+ fixup_arm_ldst_abs_12,
// 10-bit PC relative relocation for symbol addresses where the lower 2 bits
// are not encoded (so it's encoded as an 8-bit immediate).
fixup_thumb_adr_pcrel_10,
diff --git a/llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp b/llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
index 2396412996e1a..ced48ccc98834 100644
--- a/llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
+++ b/llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
@@ -977,41 +977,45 @@ getAddrModeImm12OpValue(const MCInst &MI, unsigned OpIdx,
// {17-13} = reg
// {12} = (U)nsigned (add == '1', sub == '0')
// {11-0} = imm12
- unsigned Reg, Imm12;
+ unsigned Reg = 0, Imm12 = 0;
bool isAdd = true;
// If The first operand isn't a register, we have a label reference.
const MCOperand &MO = MI.getOperand(OpIdx);
- if (!MO.isReg()) {
- Reg = CTX.getRegisterInfo()->getEncodingValue(ARM::PC); // Rn is PC.
- Imm12 = 0;
-
- if (MO.isExpr()) {
- const MCExpr *Expr = MO.getExpr();
- isAdd = false ; // 'U' bit is set as part of the fixup.
-
- MCFixupKind Kind;
- if (isThumb2(STI))
- Kind = MCFixupKind(ARM::fixup_t2_ldst_pcrel_12);
- else
- Kind = MCFixupKind(ARM::fixup_arm_ldst_pcrel_12);
- Fixups.push_back(MCFixup::create(0, Expr, Kind, MI.getLoc()));
-
- ++MCNumCPRelocations;
- } else {
- Reg = ARM::PC;
- int32_t Offset = MO.getImm();
- if (Offset == INT32_MIN) {
- Offset = 0;
- isAdd = false;
- } else if (Offset < 0) {
- Offset *= -1;
- isAdd = false;
- }
- Imm12 = Offset;
+ if (MO.isReg()) {
+ const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
+ if (MO1.isImm()) {
+ isAdd = EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm12, Fixups, STI);
+ } else if (MO1.isExpr()) {
+ assert(!isThumb(STI) && !isThumb2(STI) &&
+ "Thumb mode requires
diff erent encoding");
+ Reg = CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
+ isAdd = false; // 'U' bit is set as part of the fixup.
+ MCFixupKind Kind = MCFixupKind(ARM::fixup_arm_ldst_abs_12);
+ Fixups.push_back(MCFixup::create(0, MO1.getExpr(), Kind, MI.getLoc()));
}
- } else
- isAdd = EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm12, Fixups, STI);
+ } else if (MO.isExpr()) {
+ Reg = CTX.getRegisterInfo()->getEncodingValue(ARM::PC); // Rn is PC.
+ isAdd = false; // 'U' bit is set as part of the fixup.
+ MCFixupKind Kind;
+ if (isThumb2(STI))
+ Kind = MCFixupKind(ARM::fixup_t2_ldst_pcrel_12);
+ else
+ Kind = MCFixupKind(ARM::fixup_arm_ldst_pcrel_12);
+ Fixups.push_back(MCFixup::create(0, MO.getExpr(), Kind, MI.getLoc()));
+ ++MCNumCPRelocations;
+ } else {
+ Reg = ARM::PC;
+ int32_t Offset = MO.getImm();
+ if (Offset == INT32_MIN) {
+ Offset = 0;
+ isAdd = false;
+ } else if (Offset < 0) {
+ Offset *= -1;
+ isAdd = false;
+ }
+ Imm12 = Offset;
+ }
uint32_t Binary = Imm12 & 0xfff;
// Immediate is always encoded as positive. The 'U' bit controls add vs sub.
if (isAdd)
diff --git a/llvm/test/MC/ARM/arm-memory-instructions-immediate.s b/llvm/test/MC/ARM/arm-memory-instructions-immediate.s
new file mode 100644
index 0000000000000..eb6d815d16b24
--- /dev/null
+++ b/llvm/test/MC/ARM/arm-memory-instructions-immediate.s
@@ -0,0 +1,25 @@
+// RUN: llvm-mc -triple=armv7 -filetype=obj %s | llvm-objdump --triple=armv7 -d - | FileCheck %s
+// RUN: not llvm-mc -triple=armv7 -filetype=obj --defsym=ERR=1 < %s -o /dev/null 2>&1 | FileCheck --check-prefix=ERR %s
+
+ .syntax unified
+// Check that the assembler accepts the result of symbolic expressions as the
+// immediate operand in load and stores.
+0:
+// CHECK-LABEL: foo
+ .space 1024
+1:
+foo:
+ ldr r0, [r1, #(1b - 0b)]
+// CHECK-NEXT: ldr r0, [r1, #1024]
+ ldr r0, [r1, #(0b - 1b)]
+// CHECK-NEXT: ldr r0, [r1, #-1024]
+ ldrb r0, [r1, #(1b-0b)]
+// CHECK-NEXT: ldrb r0, [r1, #1024]
+ str r0, [r1, #(1b-0b)]
+// CHECK-NEXT: str r0, [r1, #1024]
+ strb r0, [r1, #(1b-0b)]
+// CHECK-NEXT: strb r0, [r1, #1024]
+.ifdef ERR
+ str r0, [r1, 1b]
+// ERR:[[#@LINE-1]]:5: error: unsupported relocation on symbol
+.endif
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