[PATCH] D100288: [RISCV] Add vector types to GPR for P extension and explict type to codegen patterns

[Craig Topper via Phabricator via llvm-commits]

craig.topper added a comment.

In D100288#2683472 <https://reviews.llvm.org/D100288#2683472>, @jrtc27 wrote:

> Surely some of this can be inferred by TableGen? This is rather disruptive (especially with my downstream hat on...).

Tablegen was inferring all of these because GPR only contained 1 type in each HwMode. Once you add other types, it can't infer anymore. For RISCVISD nodes we can put XLenVT into the SDTypeProfiles, but for anything using target independent SDNodes, the SDTypeProfiles aren't strong enough. Most of the target independent nodes work on vectors so tablegen doesn't know if you're trying to pattern match vectors or scalars.

I asked for this change rather than adding a P specific GPR regclass because I don't think we should have 2 register classes with identical spill and size information and different legal type lists. MCRegisterInfo ends up thinking they are subclasses of each other which is kind of odd.


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  https://reviews.llvm.org/D100288/new/

https://reviews.llvm.org/D100288