[PATCH] D100304: [AArch64][NEON] Match (or (and -a b) (and (a+1) b)) => bit select

[Bradley Smith via Phabricator via llvm-commits]

bsmith created this revision.
bsmith added reviewers: joechrisellis, peterwaller-arm, paulwalker-arm, david-arm.
Herald added subscribers: danielkiss, hiraditya, kristof.beyls.
bsmith requested review of this revision.
Herald added a project: LLVM.
Herald added a subscriber: llvm-commits.

With this patch vbslq_f32(vnegq_s32(a), b, c) lowers to a BIT instruction.

Co-authored-by: Paul Walker <paul.walker at arm.com>


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D100304

Files:
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/test/CodeGen/AArch64/neon-bitselect.ll

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