[llvm] f2593a0 - [AArch64][SVE] Remove redundant PTEST of MATCH/NMATCH results

[Bradley Smith via llvm-commits]

Author: Bradley Smith
Date: 2021-04-12T12:55:00+01:00
New Revision: f2593a0bd1b2b0da40de2400822469f85c56ac92

URL: https://github.com/llvm/llvm-project/commit/f2593a0bd1b2b0da40de2400822469f85c56ac92
DIFF: https://github.com/llvm/llvm-project/commit/f2593a0bd1b2b0da40de2400822469f85c56ac92.diff

LOG: [AArch64][SVE] Remove redundant PTEST of MATCH/NMATCH results

Co-authored-by: Paul Walker <paul.walker at arm.com>

Differential Revision: https://reviews.llvm.org/D99584

Added: 
    llvm/test/CodeGen/AArch64/sve-ptest-removal-match.ll

Modified: 
    llvm/lib/Target/AArch64/SVEInstrFormats.td

Removed: 
    


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diff  --git a/llvm/lib/Target/AArch64/SVEInstrFormats.td b/llvm/lib/Target/AArch64/SVEInstrFormats.td
index 2d3aa10b8c1e..eba9379ac030 100644
--- a/llvm/lib/Target/AArch64/SVEInstrFormats.td
+++ b/llvm/lib/Target/AArch64/SVEInstrFormats.td
@@ -7513,6 +7513,7 @@ class sve2_char_match<bit sz, bit opc, string asm,
   let Inst{3-0}   = Pd;
 
   let Defs = [NZCV];
+  let isPTestLike = 1;
 }
 
 multiclass sve2_char_match<bit opc, string asm, SDPatternOperator op> {

diff  --git a/llvm/test/CodeGen/AArch64/sve-ptest-removal-match.ll b/llvm/test/CodeGen/AArch64/sve-ptest-removal-match.ll
new file mode 100644
index 000000000000..417b55bf3a3e
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/sve-ptest-removal-match.ll
@@ -0,0 +1,38 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=aarch64--linux-gnu -mattr=+sve2 %s -o - | FileCheck %s
+
+;
+; MATCH
+;
+
+define i32 @match_nxv16i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {
+; CHECK-LABEL: match_nxv16i8:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    match p0.b, p0/z, z0.b, z1.b
+; CHECK-NEXT:    cset w0, ne
+; CHECK-NEXT:    ret
+  %1 = tail call <vscale x 16 x i1> @llvm.aarch64.sve.match.nxv16i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b)
+  %2 = tail call i1 @llvm.aarch64.sve.ptest.any(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %1)
+  %conv = zext i1 %2 to i32
+  ret i32 %conv
+}
+
+;
+; NMATCH
+;
+
+define i32 @nmatch_nxv16i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {
+; CHECK-LABEL: nmatch_nxv16i8:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    nmatch p0.b, p0/z, z0.b, z1.b
+; CHECK-NEXT:    cset w0, ne
+; CHECK-NEXT:    ret
+  %1 = tail call <vscale x 16 x i1> @llvm.aarch64.sve.nmatch.nxv16i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b)
+  %2 = tail call i1 @llvm.aarch64.sve.ptest.any(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %1)
+  %conv = zext i1 %2 to i32
+  ret i32 %conv
+}
+
+declare <vscale x 16 x i1> @llvm.aarch64.sve.match.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>)
+declare <vscale x 16 x i1> @llvm.aarch64.sve.nmatch.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>)
+declare i1 @llvm.aarch64.sve.ptest.any(<vscale x 16 x i1>, <vscale x 16 x i1>)