[PATCH] D100280: [RISCV] Implement COPY for Zvlsseg registers

[Hsiangkai Wang via Phabricator via llvm-commits]

HsiangKai added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVInstrInfo.cpp:133
   unsigned Opc;
   bool IsScalableVector = false;
+  unsigned NF = 1;
----------------
Registers for Zvlsseg are also scalable vector. How about to set `IsScalableVector` to true by default and turn it off for scalar register classes. (Refer to storeRegToStackSlot()).


================
Comment at: llvm/lib/Target/RISCV/RISCVInstrInfo.cpp:214
 
-  if (IsScalableVector)
+  if (NF > 1) {
+    const TargetRegisterInfo *TRI = STI.getRegisterInfo();
----------------
How about

```
If (IsScalableVector) {
  if (NF == 1) {
    // processing scalable vector registers.
  } else {
    // processing Zvlsseg registers.
  }
} else {
  // processing scalar registers
}
```


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D100280/new/

https://reviews.llvm.org/D100280