[PATCH] D100280: [RISCV] Implement COPY for Zvlsseg registers

[ShihPo Hung via Phabricator via llvm-commits]

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When copying Zvlsseg register tuples, we split the COPY into NF whole register moves
as below:

      
  $v10m2_v12m2 = COPY $v4m2_v6m2 # NF = 2

>
=

  $v10m2 = PseudoVMV2R_V $v4m2
  $v12m2 = PseudoVMV2R_V $v6m2
      

This patch copies forwardCopyWillClobberTuple from AArch64 to check
register overlapping.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D100280

Files:
  llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
  llvm/test/CodeGen/RISCV/rvv/zvlsseg-copy.mir

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