[PATCH] D100115: [RISCV] Add missing part of instruction vmsge {u}. VX

[Hsiangkai Wang via Phabricator via llvm-commits]

HsiangKai added a comment.

In D100115#2680063 <https://reviews.llvm.org/D100115#2680063>, @craig.topper wrote:

> In D100115#2678857 <https://reviews.llvm.org/D100115#2678857>, @HsiangKai wrote:
>
>> In D100115#2678655 <https://reviews.llvm.org/D100115#2678655>, @craig.topper wrote:
>>
>>> In D100115#2678649 <https://reviews.llvm.org/D100115#2678649>, @HsiangKai wrote:
>>>
>>>> Do we need this case? Case 4 is any vd. It means (vd == v0) || (vd != v0), right? These two cases are already covered by case 2 and case 3.
>>>
>>> I think this is the case that a temp register is provided and the destination isn't v0. The user probably should use case 2 by not providing the temp register. But if they give the temp register should we accept it and match the spec or error for the destination not being v0(what we currently do)?
>>
>> If the destination is not v0, case 2 is better than case 4. There should be no need to provide the temp register. I think the case 4 is useful when we could not determine vd is v0 or not, but it should not be the case in AsmParser. The registers in MCInst should be physical registers.
>
> What does the GNU assembler do?
>
> Can someone write inline assembly that requires this? If they let the compiler allocate the registers for the inline assembly we would need to support any register.

Got it. Maybe we need this pattern for inline asm. I have no strong opinion to oppose this patch. Just curious when we need it.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D100115/new/

https://reviews.llvm.org/D100115