[PATCH] D99272: [AArch64] Adds a pre-indexed paired Load/Store optimization for LDR-STR.

[Stelios Ioannou via Phabricator via llvm-commits]

stelios-arm updated this revision to Diff 336390.
stelios-arm marked an inline comment as done.
stelios-arm retitled this revision from "[AArch64] Adds a pre-indexed Load/Store optimization for LDRQ-STRQ." to "[AArch64] Adds a pre-indexed paired Load/Store optimization for LDR-STR.".
stelios-arm edited the summary of this revision.
stelios-arm added a comment.

1. Added all the various forms of `STR<>pre`/`LDR<>pre`.
2. Added additional test cases for the MIR tests to cover the various forms of  `STR<>pre`/`LDR<>pre`.
3. Added constraints so that it optimizes cases where the offset of the second `LDR/STR<>ui` is equal to the size of the destination register. Additionally, it only optimizes cases where the base register of the pre-index `LDR/STRpre<>` is not used or modified.
4. Did a bootstrap build and ran the llvm test-suite on an `AArch64` machine. Both the test-suite and regression tests results in no errors.
5. Currently there is a hack to avoid the `memoperands_empty()` check for `LDR<>pre` instructions. This is because they are missing the load memory operand. See below:

  early-clobber renamable $x1, renamable $w0 = LDRWpre killed renamable $x1, 20

instead it should look something similar to:

  early-clobber renamable $x1, renamable $w0 = LDRWpre killed renamable $x1, 20 :: (load 4)

This is going to be addressed in another patch, and then this patch will be updated to remove the hack that is in place.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D99272/new/

https://reviews.llvm.org/D99272

Files:
  llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
  llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp
  llvm/test/CodeGen/AArch64/arm64-memset-inline.ll
  llvm/test/CodeGen/AArch64/ldrpre-ldr-merge.mir
  llvm/test/CodeGen/AArch64/strpre-str-merge.mir

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