[PATCH] D97264: [RISCV] Define types for Zvlsseg.

[Hsiangkai Wang via Phabricator via llvm-commits]

HsiangKai updated this revision to Diff 336320.
HsiangKai added a comment.

Put element types in the macro and use them to create RecordType directly.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D97264/new/

https://reviews.llvm.org/D97264

Files:
  clang/include/clang/AST/ASTContext.h
  clang/include/clang/Basic/Builtins.def
  clang/include/clang/Basic/RISCVVTypes.def
  clang/lib/AST/ASTContext.cpp
  clang/lib/Sema/Sema.cpp
  clang/test/Sema/riscv-types.c

-------------- next part --------------
A non-text attachment was scrubbed...
Name: D97264.336320.patch
Type: text/x-patch
Size: 44421 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20210409/96a409f3/attachment.bin>