[PATCH] D100115: [RISCV] Add missing part of instruction vmsge {u}. VX

[Craig Topper via Phabricator via llvm-commits]

craig.topper added a comment.

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Comment at: llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp:2397
                             .addReg(RISCV::V0));
-  } else if (Inst.getNumOperands() == 5) {
+  } else if (Inst.getNumOperands() == 5 && Inst.getOperand(0).getReg() == RISCV::V0) {
     // masked va >= x, vd == v0
----------------
Please wrap this line as clang-format says.


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Comment at: llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp:2416
+  } else if (Inst.getNumOperands() == 5){
+  //masked va >= x, any vd
+  //pseudoinstruction: vmsge{u}.vx vd, va, x, v0.t, vt
----------------
Please indent these comments as the clang-format says.


Repository:
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  https://reviews.llvm.org/D100115/new/

https://reviews.llvm.org/D100115