[PATCH] D100050: [AIX] Remove unused vector registers from allocation order in the default AltiVec ABI

[Zarko Todorovski via Phabricator via llvm-commits]

ZarkoCA added a comment.

In D100050#2677005 <https://reviews.llvm.org/D100050#2677005>, @jsji wrote:

> Thanks.
>
>> 1. Applying the fix in getReservedRegs //should// work, however, removing from the allocation order is technically more correct since they are not actually reserved for any use. Instead they cannot be used at all.
>
> I am not sure why it is *technically more correct* to change allocation order instead of *reservering reserved reg in designed API*.
>
> I believe these regs are exactly what *Reserved Register* defines.
>
> According to AIX ABI: https://www.ibm.com/docs/en/aix/7.2?topic=concepts-aix-vector-programming
>
>   VR20:31	Reserved (default mode)
>   Nonvolatile (extended ABI mode)
>   
>   When the default Vector enabled mode is used, these registers are reserved and must not be used.
>   In the extended ABI vector enabled mode, these registers are nonvolatile and their values are preserved across function calls
>
> And the `getReservedRegs` API is:
>
>   /// Returns a bitset indexed by physical register number indicating if a
>   /// register is a special register that has particular uses and should be
>   /// considered unavailable at all times, e.g. stack pointer, return address.
>   /// A reserved register:
>   /// - is not allocatable
>   /// - is considered always live
>   /// - is ignored by liveness tracking
>   /// It is often necessary to reserve the super registers of a reserved
>   /// register as well, to avoid them getting allocated indirectly. You may use
>   /// markSuperRegs() and checkAllSuperRegsMarked() in this case.
>   virtual BitVector getReservedRegs(const MachineFunction &MF) const = 0;
>
> My understanding of `has particular uses` is that compiler will work well if there is some special (or unexpected) use of these regs,
> but it does not mean that you *HAVE* to have some use in compiler...

I understand what you mean.  And a further point toward your argument that you made in our offline discussions is that this is how we treat all AltiVec registers for a target that does not support it, that is, we mark all of them as reserved.


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