[llvm] e184eea - [AMDGPU] Add some implicit uses to tests. NFC.

[Jay Foad via llvm-commits]

Author: Jay Foad
Date: 2021-04-08T16:37:48+01:00
New Revision: e184eeaa3ba124722684dcaece92e712f2484d9b

URL: https://github.com/llvm/llvm-project/commit/e184eeaa3ba124722684dcaece92e712f2484d9b
DIFF: https://github.com/llvm/llvm-project/commit/e184eeaa3ba124722684dcaece92e712f2484d9b.diff

LOG: [AMDGPU] Add some implicit uses to tests. NFC.

This is just to stop a future patch from optimizing away the things that
we actually want to check for.

Added: 
    

Modified: 
    llvm/test/CodeGen/AMDGPU/fold-cndmask-wave32.mir
    llvm/test/CodeGen/AMDGPU/fold-cndmask.mir
    llvm/test/CodeGen/AMDGPU/fold-operands-order.mir
    llvm/test/CodeGen/AMDGPU/fold-readlane.mir

Removed: 
    


################################################################################
diff  --git a/llvm/test/CodeGen/AMDGPU/fold-cndmask-wave32.mir b/llvm/test/CodeGen/AMDGPU/fold-cndmask-wave32.mir
index c22e0259a892..25e926f06aa9 100644
--- a/llvm/test/CodeGen/AMDGPU/fold-cndmask-wave32.mir
+++ b/llvm/test/CodeGen/AMDGPU/fold-cndmask-wave32.mir
@@ -16,5 +16,5 @@ body:             |
     %1:sreg_32 = S_MOV_B32 0
     %2:vgpr_32 = COPY %1:sreg_32
     %3:vgpr_32 = V_CNDMASK_B32_e64 0, %1:sreg_32, 0, %2:vgpr_32, %0:sreg_32_xm0_xexec, implicit $exec
-
+    S_ENDPGM 0, implicit %3
 ...

diff  --git a/llvm/test/CodeGen/AMDGPU/fold-cndmask.mir b/llvm/test/CodeGen/AMDGPU/fold-cndmask.mir
index f2072c0fa4f2..087ee4c12c98 100644
--- a/llvm/test/CodeGen/AMDGPU/fold-cndmask.mir
+++ b/llvm/test/CodeGen/AMDGPU/fold-cndmask.mir
@@ -30,5 +30,5 @@ body:             |
     %6 = V_CNDMASK_B32_e64 0, %5, 0, 0, %0, implicit $exec
     $vcc = IMPLICIT_DEF
     %7 = V_CNDMASK_B32_e32 %3, %3, implicit $exec, implicit $vcc
-
+    S_ENDPGM 0, implicit %1, implicit %2, implicit %4, implicit %6, implicit %7
 ...

diff  --git a/llvm/test/CodeGen/AMDGPU/fold-operands-order.mir b/llvm/test/CodeGen/AMDGPU/fold-operands-order.mir
index a4ded7f946bc..f8c6547bf6ea 100644
--- a/llvm/test/CodeGen/AMDGPU/fold-operands-order.mir
+++ b/llvm/test/CodeGen/AMDGPU/fold-operands-order.mir
@@ -31,6 +31,7 @@ body:             |
 
     %2 = COPY %1
     %3 = V_XOR_B32_e64 killed %2, undef %0, implicit $exec
+    S_NOP 0, implicit %3
 
   bb.2:
     successors: %bb.1

diff  --git a/llvm/test/CodeGen/AMDGPU/fold-readlane.mir b/llvm/test/CodeGen/AMDGPU/fold-readlane.mir
index 711df3580429..0bda14e0ff91 100644
--- a/llvm/test/CodeGen/AMDGPU/fold-readlane.mir
+++ b/llvm/test/CodeGen/AMDGPU/fold-readlane.mir
@@ -9,6 +9,7 @@ body:             |
   bb.0:
     %0:vgpr_32 = V_MOV_B32_e32 123, implicit $exec
     %1:sreg_32_xm0 = V_READFIRSTLANE_B32 %0, implicit $exec
+    S_NOP 0, implicit %1
 ...
 
 # GCN-LABEL: name: fold-imm-readfirstlane-readfirstlane{{$}}
@@ -26,7 +27,7 @@ body:             |
     %1:sreg_32_xm0 = V_READFIRSTLANE_B32 %0, implicit $exec
     %2:vgpr_32 = COPY %1
     %3:sreg_32_xm0 = V_READFIRSTLANE_B32 %2, implicit $exec
-
+    S_NOP 0, implicit %3
 ...
 
 
@@ -43,7 +44,7 @@ body:             |
     %0:sreg_32_xm0 = COPY $sgpr10
     %1:vgpr_32 = COPY %0
     %2:sreg_32_xm0 = V_READFIRSTLANE_B32 %1, implicit $exec
-
+    S_NOP 0, implicit %2
 ...
 
 # GCN-LABEL: name: no-fold-copy-readfirstlane-physreg0{{$}}
@@ -233,6 +234,7 @@ body:             |
     liveins: $vgpr0, $sgpr0_sgpr1
     %0:vgpr_32 = V_MOV_B32_e32 123, implicit $exec
     %1:sreg_32_xm0 = V_READLANE_B32 %0, 0, implicit $exec
+    S_NOP 0, implicit %1
 ...
 
 # GCN-LABEL: name: fold-imm-readlane-src1{{$}}
@@ -268,6 +270,7 @@ body:             |
     %2:vreg_64 = REG_SEQUENCE %0:vgpr_32, %subreg.sub0, killed %1:vgpr_32, %subreg.sub1
     %3:sgpr_32 = V_READFIRSTLANE_B32 %2.sub0:vreg_64, implicit $exec
     %4:sgpr_32 = V_READFIRSTLANE_B32 %2.sub1:vreg_64, implicit $exec
+    S_NOP 0, implicit %3, implicit %4
 ...
 
 # Constant for subreg1
@@ -289,6 +292,7 @@ body:             |
     %2:vreg_64 = REG_SEQUENCE %1:vgpr_32, %subreg.sub0, killed %0:vgpr_32, %subreg.sub1
     %3:sgpr_32 = V_READFIRSTLANE_B32 %2.sub0:vreg_64, implicit $exec
     %4:sgpr_32 = V_READFIRSTLANE_B32 %2.sub1:vreg_64, implicit $exec
+    S_NOP 0, implicit %3, implicit %4
 ...
 
 # Different constant regs for each subreg
@@ -308,6 +312,7 @@ body:             |
     %2:vreg_64 = REG_SEQUENCE %0:vgpr_32, %subreg.sub0, killed %1:vgpr_32, %subreg.sub1
     %3:sgpr_32 = V_READFIRSTLANE_B32 %2.sub0:vreg_64, implicit $exec
     %4:sgpr_32 = V_READFIRSTLANE_B32 %2.sub1:vreg_64, implicit $exec
+    S_NOP 0, implicit %3, implicit %4
 ...
 
 # Same constant reg for each subreg, so there are multiple constant uses
@@ -327,6 +332,7 @@ body:             |
     %2:vreg_64 = REG_SEQUENCE %0:vgpr_32, %subreg.sub0, killed %1:vgpr_32, %subreg.sub1
     %3:sgpr_32 = V_READFIRSTLANE_B32 %2.sub0:vreg_64, implicit $exec
     %4:sgpr_32 = V_READFIRSTLANE_B32 %2.sub1:vreg_64, implicit $exec
+    S_NOP 0, implicit %3, implicit %4
 ...
 
 # FIXME: This should fold