[PATCH] D99294: [LV] Track incoming values for reductions in recipe (NFC).

[Florian Hahn via Phabricator via llvm-commits]

fhahn updated this revision to Diff 336113.
fhahn added a comment.

Rebased. I also put up 2 additional patches that make use of the operand for the incoming value of the backedge in more places: D100102 <https://reviews.llvm.org/D100102> & D100113 <https://reviews.llvm.org/D100113>.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D99294/new/

https://reviews.llvm.org/D99294

Files:
  llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
  llvm/test/Transforms/LoopVectorize/vplan-printing.ll


Index: llvm/test/Transforms/LoopVectorize/vplan-printing.ll
===================================================================
--- llvm/test/Transforms/LoopVectorize/vplan-printing.ll
+++ llvm/test/Transforms/LoopVectorize/vplan-printing.ll
@@ -79,7 +79,7 @@
 ; CHECK:      VPlan 'Initial VPlan for VF={4},UF>=1' {
 ; CHECK-NEXT: for.body:
 ; CHECK-NEXT:   WIDEN-INDUCTION %iv = phi %iv.next, 0
-; CHECK-NEXT:   WIDEN-PHI %red = phi %red.next, 0.000000e+00
+; CHECK-NEXT:   WIDEN-PHI ir<%red> = phi ir<0.000000e+00>, ir<%red.next>
 ; CHECK-NEXT:   CLONE ir<%arrayidx> = getelementptr ir<%y>, ir<%iv>
 ; CHECK-NEXT:   WIDEN ir<%lv> = load ir<%arrayidx>
 ; CHECK-NEXT:   REDUCE ir<%red.next> = ir<%red> + reduce.fadd (ir<%lv>)
Index: llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
===================================================================
--- llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
+++ llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
@@ -4299,17 +4299,15 @@
 
   // Reductions do not have to start at zero. They can start with
   // any loop invariant values.
-  BasicBlock *Latch = OrigLoop->getLoopLatch();
-  Value *LoopVal = OrigPhi->getIncomingValueForBlock(Latch);
-
   for (unsigned Part = 0; Part < UF; ++Part) {
-    Value *VecRdxPhi = State.get(PhiR->getVPValue(), Part);
-    Value *Val = State.get(State.Plan->getVPValue(LoopVal), Part);
+    Value *VecRdxPhi = State.get(PhiR->getVPValue(0), Part);
+    Value *Val = State.get(PhiR->getOperand(1), Part);
     if (IsInLoopReductionPhi && useOrderedReductions(RdxDesc) &&
         State.VF.isVector())
-      Val = State.get(State.Plan->getVPValue(LoopVal), UF - 1);
-    cast<PHINode>(VecRdxPhi)
-      ->addIncoming(Val, LI->getLoopFor(LoopVectorBody)->getLoopLatch());
+      Val = State.get(PhiR->getOperand(1), UF - 1);
+
+    cast<PHINode>(VecRdxPhi)->addIncoming(
+        Val, LI->getLoopFor(LoopVectorBody)->getLoopLatch());
   }
 
   // Before each round, move the insertion point right between
@@ -8847,6 +8845,18 @@
     RecipeBuilder.recordRecipeOf(Entry.first);
     RecipeBuilder.recordRecipeOf(Entry.second);
   }
+
+  SmallVector<PHINode *, 4> PhisToFix;
+  BasicBlock *OrigLatch = OrigLoop->getLoopLatch();
+  for (PHINode &Phi : OrigLoop->getHeader()->phis()) {
+    if (!Legal->isReductionVariable(&Phi))
+      continue;
+    PhisToFix.push_back(&Phi);
+    RecipeBuilder.recordRecipeOf(&Phi);
+    RecipeBuilder.recordRecipeOf(
+        cast<Instruction>(Phi.getIncomingValueForBlock(OrigLatch)));
+  }
+
   for (auto &Reduction : CM.getInLoopReductionChains()) {
     PHINode *Phi = Reduction.first;
     RecurKind Kind = Legal->getReductionVars()[Phi].getRecurrenceKind();
@@ -8954,6 +8964,14 @@
     }
   }
 
+  for (PHINode *PN : PhisToFix) {
+    VPWidenPHIRecipe *R = cast<VPWidenPHIRecipe>(RecipeBuilder.getRecipe(PN));
+    VPRecipeBase *IncR = RecipeBuilder.getRecipe(
+        cast<Instruction>(PN->getIncomingValueForBlock(OrigLatch)));
+    assert(IncR->getNumDefinedValues() == 1);
+    R->addOperand(IncR->getVPValue(0));
+  }
+
   // Discard empty dummy pre-entry VPBasicBlock. Note that other VPBasicBlocks
   // may also be empty, such as the last one VPBB, reflecting original
   // basic-blocks with no recipes.


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