[PATCH] D99083: [RISCV] Introduce floating point control and state registers

[Serge Pavlov via Phabricator via llvm-commits]

sepavloff updated this revision to Diff 336010.
sepavloff added a comment.

Use zero for encoding of FFLAGS, FRM and FCSR. Rebased.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D99083/new/

https://reviews.llvm.org/D99083

Files:
  llvm/lib/Target/RISCV/RISCVInstrInfo.td
  llvm/lib/Target/RISCV/RISCVInstrInfoF.td
  llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
  llvm/lib/Target/RISCV/RISCVRegisterInfo.td
  llvm/lib/Target/RISCV/RISCVSystemOperands.td

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