[llvm] 65b1103 - [RISCV] DAG nodes and pseudo instructions for CSR access
Serge Pavlov via llvm-commits
llvm-commits at lists.llvm.org
Wed Apr 7 20:37:39 PDT 2021
Author: Serge Pavlov
Date: 2021-04-08T10:36:36+07:00
New Revision: 65b1103798df7bc84137766d813315b4cc54df3e
URL: https://github.com/llvm/llvm-project/commit/65b1103798df7bc84137766d813315b4cc54df3e
DIFF: https://github.com/llvm/llvm-project/commit/65b1103798df7bc84137766d813315b4cc54df3e.diff
LOG: [RISCV] DAG nodes and pseudo instructions for CSR access
New custom DAG nodes were added to represent operations on CSR. These
nodes are lowered to corresponding pseudo instruction. Using the pseudo
instructions allows to specify different scheduling information for
operations on different system registers. It also make possible to
specify dependencies of instructions on specific system registers.
Differential Revision: https://reviews.llvm.org/D98936
Added:
Modified:
llvm/lib/Target/RISCV/RISCVISelLowering.cpp
llvm/lib/Target/RISCV/RISCVISelLowering.h
llvm/lib/Target/RISCV/RISCVInstrInfo.td
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index e9c1a4893834..df98b52f7973 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -7121,6 +7121,9 @@ const char *RISCVTargetLowering::getTargetNodeName(unsigned Opcode) const {
NODE_NAME_CASE(VZEXT_VL)
NODE_NAME_CASE(VLE_VL)
NODE_NAME_CASE(VSE_VL)
+ NODE_NAME_CASE(READ_CSR)
+ NODE_NAME_CASE(WRITE_CSR)
+ NODE_NAME_CASE(SWAP_CSR)
}
// clang-format on
return nullptr;
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.h b/llvm/lib/Target/RISCV/RISCVISelLowering.h
index 5eee10e92fd3..38b15c7b7143 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.h
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.h
@@ -227,6 +227,22 @@ enum NodeType : unsigned {
VSEXT_VL,
VZEXT_VL,
+ // Reads value of CSR.
+ // The first operand is a chain pointer. The second specifies address of the
+ // required CSR. Two results are produced, the read value and the new chain
+ // pointer.
+ READ_CSR,
+ // Write value to CSR.
+ // The first operand is a chain pointer, the second specifies address of the
+ // required CSR and the third is the value to write. The result is the new
+ // chain pointer.
+ WRITE_CSR,
+ // Read and write value of CSR.
+ // The first operand is a chain pointer, the second specifies address of the
+ // required CSR and the third is the value to write. Two results are produced,
+ // the value read before the modification and the new chain pointer.
+ SWAP_CSR,
+
// Memory opcodes start here.
VLE_VL = ISD::FIRST_TARGET_MEMORY_OPCODE,
VSE_VL,
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
index b6a4d2ea85fa..87a54cc8b6b3 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
@@ -28,6 +28,10 @@ def SDT_RISCVSelectCC : SDTypeProfile<1, 5, [SDTCisSameAs<1, 2>,
def SDT_RISCVBrCC : SDTypeProfile<0, 4, [SDTCisSameAs<0, 1>,
SDTCisVT<2, OtherVT>,
SDTCisVT<3, OtherVT>]>;
+def SDT_RISCVReadCSR : SDTypeProfile<1, 1, [SDTCisInt<0>, SDTCisInt<1>]>;
+def SDT_RISCVWriteCSR : SDTypeProfile<0, 2, [SDTCisInt<0>, SDTCisInt<1>]>;
+def SDT_RISCVSwapCSR : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisInt<1>,
+ SDTCisInt<2>]>;
def SDT_RISCVReadCycleWide : SDTypeProfile<2, 0, [SDTCisVT<0, i32>,
SDTCisVT<1, i32>]>;
def SDT_RISCVIntBinOpW : SDTypeProfile<1, 2, [
@@ -61,6 +65,12 @@ def riscv_tail : SDNode<"RISCVISD::TAIL", SDT_RISCVCall,
def riscv_sllw : SDNode<"RISCVISD::SLLW", SDT_RISCVIntBinOpW>;
def riscv_sraw : SDNode<"RISCVISD::SRAW", SDT_RISCVIntBinOpW>;
def riscv_srlw : SDNode<"RISCVISD::SRLW", SDT_RISCVIntBinOpW>;
+def riscv_read_csr : SDNode<"RISCVISD::READ_CSR", SDT_RISCVReadCSR,
+ [SDNPHasChain]>;
+def riscv_write_csr : SDNode<"RISCVISD::WRITE_CSR", SDT_RISCVWriteCSR,
+ [SDNPHasChain]>;
+def riscv_swap_csr : SDNode<"RISCVISD::SWAP_CSR", SDT_RISCVSwapCSR,
+ [SDNPHasChain]>;
def riscv_read_cycle_wide : SDNode<"RISCVISD::READ_CYCLE_WIDE",
SDT_RISCVReadCycleWide,
@@ -1115,6 +1125,54 @@ def : Pat<(atomic_fence (XLenVT 7), (timm)), (FENCE 0b11, 0b11)>;
// present. This is necessary as it isn't valid to mix __atomic_* libcalls
// with inline atomic operations for the same object.
+/// Access to system registers
+
+// Helpers for defining specific operations. They are defined for each system
+// register separately. Side effect is not used because dependencies are
+// expressed via use-def properties.
+
+class ReadSysReg<SysReg SR, list<Register> Regs>
+ : Pseudo<(outs GPR:$rd), (ins),
+ [(set GPR:$rd, (riscv_read_csr (XLenVT SR.Encoding)))]>,
+ PseudoInstExpansion<(CSRRS GPR:$rd, SR.Encoding, X0)> {
+ let hasSideEffects = 0;
+ let Uses = Regs;
+}
+
+class WriteSysReg<SysReg SR, list<Register> Regs>
+ : Pseudo<(outs), (ins GPR:$val),
+ [(riscv_write_csr (XLenVT SR.Encoding), GPR:$val)]>,
+ PseudoInstExpansion<(CSRRW X0, SR.Encoding, GPR:$val)> {
+ let hasSideEffects = 0;
+ let Defs = Regs;
+}
+
+class WriteSysRegImm<SysReg SR, list<Register> Regs>
+ : Pseudo<(outs), (ins uimm5:$val),
+ [(riscv_write_csr (XLenVT SR.Encoding), uimm5:$val)]>,
+ PseudoInstExpansion<(CSRRWI X0, SR.Encoding, uimm5:$val)> {
+ let hasSideEffects = 0;
+ let Defs = Regs;
+}
+
+class SwapSysReg<SysReg SR, list<Register> Regs>
+ : Pseudo<(outs GPR:$rd), (ins GPR:$val),
+ [(set GPR:$rd, (riscv_swap_csr (XLenVT SR.Encoding), GPR:$val))]>,
+ PseudoInstExpansion<(CSRRW GPR:$rd, SR.Encoding, GPR:$val)> {
+ let hasSideEffects = 0;
+ let Uses = Regs;
+ let Defs = Regs;
+}
+
+class SwapSysRegImm<SysReg SR, list<Register> Regs>
+ : Pseudo<(outs GPR:$rd), (ins uimm5:$val),
+ [(set GPR:$rd, (riscv_swap_csr (XLenVT SR.Encoding), uimm5:$val))]>,
+ PseudoInstExpansion<(CSRRWI GPR:$rd, SR.Encoding, uimm5:$val)> {
+ let hasSideEffects = 0;
+ let Uses = Regs;
+ let Defs = Regs;
+}
+
/// Other pseudo-instructions
// Pessimistically assume the stack pointer will be clobbered
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