[PATCH] D100035: [RISCV] Add scalable offset under very large stack size.

[Hsiangkai Wang via Phabricator via llvm-commits]

HsiangKai updated this revision to Diff 335984.

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D100035/new/

https://reviews.llvm.org/D100035

Files:
  llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
  llvm/test/CodeGen/RISCV/rvv/addi-scalable-offset.mir


Index: llvm/test/CodeGen/RISCV/rvv/addi-scalable-offset.mir
===================================================================
--- llvm/test/CodeGen/RISCV/rvv/addi-scalable-offset.mir
+++ llvm/test/CodeGen/RISCV/rvv/addi-scalable-offset.mir
@@ -43,6 +43,8 @@
     ; CHECK: $x10 = LUI 1048575
     ; CHECK: $x10 = ADDIW killed $x10, 1824
     ; CHECK: $x10 = ADD $x8, killed $x10
+    ; CHECK: $x11 = PseudoReadVLENB
+    ; CHECK: $x10 = SUB killed $x10, killed $x11
     ; CHECK: VS1R_V killed renamable $v25, killed renamable $x10
     ; CHECK: $x10 = PseudoReadVLENB
     ; CHECK: $x2 = ADD $x2, killed $x10
Index: llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
===================================================================
--- llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
+++ llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
@@ -213,7 +213,7 @@
     // Modify Offset and FrameReg appropriately
     Register ScratchReg = MRI.createVirtualRegister(&RISCV::GPRRegClass);
     TII->movImm(MBB, II, DL, ScratchReg, Offset.getFixed());
-    if (MI.getOpcode() == RISCV::ADDI) {
+    if (MI.getOpcode() == RISCV::ADDI && !Offset.getScalable()) {
       BuildMI(MBB, II, DL, TII->get(RISCV::ADD), MI.getOperand(0).getReg())
         .addReg(FrameReg)
         .addReg(ScratchReg, RegState::Kill);
@@ -258,6 +258,13 @@
         TII->getVLENFactoredAmount(MF, MBB, II, ScalableValue);
 
     // 2. Calculate address: FrameReg + result of multiply
+    if (MI.getOpcode() == RISCV::ADDI && !Offset.getFixed()) {
+      BuildMI(MBB, II, DL, TII->get(Opc), MI.getOperand(0).getReg())
+          .addReg(FrameReg, getKillRegState(FrameRegIsKill))
+          .addReg(FactorRegister, RegState::Kill);
+      MI.eraseFromParent();
+      return;
+    }
     Register VL = MRI.createVirtualRegister(&RISCV::GPRRegClass);
     BuildMI(MBB, II, DL, TII->get(Opc), VL)
         .addReg(FrameReg, getKillRegState(FrameRegIsKill))


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