[PATCH] D100030: [RISCV] Support OR/XOR/AND reductions on vector masks

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


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Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:3032
+  case ISD::VECREDUCE_AND:
+    // vpopc !x == 0
+    Vec = DAG.getNode(RISCVISD::VMXOR_VL, DL, ContainerVT, Vec, Mask, VL);
----------------
Should this be ~x rather than !x


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Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:3041
+  case ISD::VECREDUCE_XOR: {
+    // vpopc != 0 && vpopc != vl
+    Vec = DAG.getNode(RISCVISD::VPOPC_VL, DL, XLenVT, Vec, Mask, VL);
----------------
This doesn't make sense to me. I was thinking xor should be (vpopc & 1) != 0. Meaning it's 1 when there is an odd number of set bits.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D100030/new/

https://reviews.llvm.org/D100030