[PATCH] D100050: [AIX] Remove unused vector registers from allocation order in the default AltiVec ABI
Zarko Todorovski via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Wed Apr 7 10:27:48 PDT 2021
ZarkoCA created this revision.
ZarkoCA added reviewers: sfertile, nemanjai, jsji.
Herald added subscribers: kbarton, hiraditya.
ZarkoCA requested review of this revision.
Herald added a project: LLVM.
Herald added a subscriber: llvm-commits.
The previous implementation of the default AltiVec ABI
marked registers V20-V31 as reserved. This failed to
prevent reserved VFRC registers being allocated. In this
patch instead of marking the registers reserved we all
unallowed registers from the allocation order.
Repository:
rG LLVM Github Monorepo
https://reviews.llvm.org/D100050
Files:
llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
llvm/lib/Target/PowerPC/PPCRegisterInfo.td
llvm/test/CodeGen/PowerPC/aix-dfltabi-rsrvd-reg.ll
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