[PATCH] D100050: [AIX] Remove unused vector registers from allocation order in the default AltiVec ABI

Zarko Todorovski via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Wed Apr 7 10:27:48 PDT 2021


ZarkoCA created this revision.
ZarkoCA added reviewers: sfertile, nemanjai, jsji.
Herald added subscribers: kbarton, hiraditya.
ZarkoCA requested review of this revision.
Herald added a project: LLVM.
Herald added a subscriber: llvm-commits.

The previous implementation of the default AltiVec ABI
marked registers V20-V31 as reserved.  This failed to 
prevent reserved VFRC registers being allocated. In this
patch instead of marking the registers reserved we all
unallowed registers from the allocation order.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D100050

Files:
  llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
  llvm/lib/Target/PowerPC/PPCRegisterInfo.td
  llvm/test/CodeGen/PowerPC/aix-dfltabi-rsrvd-reg.ll

-------------- next part --------------
A non-text attachment was scrubbed...
Name: D100050.335853.patch
Type: text/x-patch
Size: 11576 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20210407/c83ce892/attachment.bin>


More information about the llvm-commits mailing list