[llvm] 302e748 - [X86] Improve optimizeCompareInstr for signed comparisons after AND/OR/XOR instructions
Simon Pilgrim via llvm-commits
llvm-commits at lists.llvm.org
Wed Apr 7 06:29:22 PDT 2021
Author: Simon Pilgrim
Date: 2021-04-07T14:28:42+01:00
New Revision: 302e7480655b0d1c1a3a629b4ef446bf77dcb01a
URL: https://github.com/llvm/llvm-project/commit/302e7480655b0d1c1a3a629b4ef446bf77dcb01a
DIFF: https://github.com/llvm/llvm-project/commit/302e7480655b0d1c1a3a629b4ef446bf77dcb01a.diff
LOG: [X86] Improve optimizeCompareInstr for signed comparisons after AND/OR/XOR instructions
Extend D94856 to handle 'and', 'or' and 'xor' instructions as well
We still fail on many i8/i16 cases as the test and the logic-op are performed on different widths
Added:
Modified:
llvm/lib/Target/X86/X86InstrInfo.cpp
llvm/test/CodeGen/X86/and-with-overflow.ll
llvm/test/CodeGen/X86/or-with-overflow.ll
llvm/test/CodeGen/X86/xor-with-overflow.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/X86/X86InstrInfo.cpp b/llvm/lib/Target/X86/X86InstrInfo.cpp
index 96af0aaab7b9..981c735c4239 100644
--- a/llvm/lib/Target/X86/X86InstrInfo.cpp
+++ b/llvm/lib/Target/X86/X86InstrInfo.cpp
@@ -4010,21 +4010,6 @@ inline static bool isDefConvertible(const MachineInstr &MI, bool &NoSignFlag,
case X86::ADD16rr: case X86::ADD8rr: case X86::ADD64rm:
case X86::ADD32rm: case X86::ADD16rm: case X86::ADD8rm:
case X86::INC64r: case X86::INC32r: case X86::INC16r: case X86::INC8r:
- case X86::AND64ri32: case X86::AND64ri8: case X86::AND32ri:
- case X86::AND32ri8: case X86::AND16ri: case X86::AND16ri8:
- case X86::AND8ri: case X86::AND64rr: case X86::AND32rr:
- case X86::AND16rr: case X86::AND8rr: case X86::AND64rm:
- case X86::AND32rm: case X86::AND16rm: case X86::AND8rm:
- case X86::XOR64ri32: case X86::XOR64ri8: case X86::XOR32ri:
- case X86::XOR32ri8: case X86::XOR16ri: case X86::XOR16ri8:
- case X86::XOR8ri: case X86::XOR64rr: case X86::XOR32rr:
- case X86::XOR16rr: case X86::XOR8rr: case X86::XOR64rm:
- case X86::XOR32rm: case X86::XOR16rm: case X86::XOR8rm:
- case X86::OR64ri32: case X86::OR64ri8: case X86::OR32ri:
- case X86::OR32ri8: case X86::OR16ri: case X86::OR16ri8:
- case X86::OR8ri: case X86::OR64rr: case X86::OR32rr:
- case X86::OR16rr: case X86::OR8rr: case X86::OR64rm:
- case X86::OR32rm: case X86::OR16rm: case X86::OR8rm:
case X86::ADC64ri32: case X86::ADC64ri8: case X86::ADC32ri:
case X86::ADC32ri8: case X86::ADC16ri: case X86::ADC16ri8:
case X86::ADC8ri: case X86::ADC64rr: case X86::ADC32rr:
@@ -4049,6 +4034,21 @@ inline static bool isDefConvertible(const MachineInstr &MI, bool &NoSignFlag,
case X86::TZCNT32rr: case X86::TZCNT32rm:
case X86::TZCNT64rr: case X86::TZCNT64rm:
return true;
+ case X86::AND64ri32: case X86::AND64ri8: case X86::AND32ri:
+ case X86::AND32ri8: case X86::AND16ri: case X86::AND16ri8:
+ case X86::AND8ri: case X86::AND64rr: case X86::AND32rr:
+ case X86::AND16rr: case X86::AND8rr: case X86::AND64rm:
+ case X86::AND32rm: case X86::AND16rm: case X86::AND8rm:
+ case X86::XOR64ri32: case X86::XOR64ri8: case X86::XOR32ri:
+ case X86::XOR32ri8: case X86::XOR16ri: case X86::XOR16ri8:
+ case X86::XOR8ri: case X86::XOR64rr: case X86::XOR32rr:
+ case X86::XOR16rr: case X86::XOR8rr: case X86::XOR64rm:
+ case X86::XOR32rm: case X86::XOR16rm: case X86::XOR8rm:
+ case X86::OR64ri32: case X86::OR64ri8: case X86::OR32ri:
+ case X86::OR32ri8: case X86::OR16ri: case X86::OR16ri8:
+ case X86::OR8ri: case X86::OR64rr: case X86::OR32rr:
+ case X86::OR16rr: case X86::OR8rr: case X86::OR64rm:
+ case X86::OR32rm: case X86::OR16rm: case X86::OR8rm:
case X86::ANDN32rr: case X86::ANDN32rm:
case X86::ANDN64rr: case X86::ANDN64rm:
case X86::BLSI32rr: case X86::BLSI32rm:
diff --git a/llvm/test/CodeGen/X86/and-with-overflow.ll b/llvm/test/CodeGen/X86/and-with-overflow.ll
index a6565d68e8d3..9f7f45202e13 100644
--- a/llvm/test/CodeGen/X86/and-with-overflow.ll
+++ b/llvm/test/CodeGen/X86/and-with-overflow.ll
@@ -119,7 +119,6 @@ define i32 @and_i32_ri(i32 %0, i32 %1) {
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NEXT: movl %eax, %ecx
; X86-NEXT: andl $-17, %ecx
-; X86-NEXT: testl %ecx, %ecx
; X86-NEXT: jle .LBB4_2
; X86-NEXT: # %bb.1:
; X86-NEXT: movl %ecx, %eax
@@ -130,7 +129,6 @@ define i32 @and_i32_ri(i32 %0, i32 %1) {
; X64: # %bb.0:
; X64-NEXT: movl %edi, %eax
; X64-NEXT: andl $-17, %eax
-; X64-NEXT: testl %eax, %eax
; X64-NEXT: cmovlel %edi, %eax
; X64-NEXT: retq
%3 = and i32 %0, -17
@@ -145,7 +143,6 @@ define i32 @and_i32_rr(i32 %0, i32 %1) {
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-NEXT: andl %eax, %ecx
-; X86-NEXT: testl %ecx, %ecx
; X86-NEXT: jle .LBB5_2
; X86-NEXT: # %bb.1:
; X86-NEXT: movl %ecx, %eax
@@ -156,7 +153,6 @@ define i32 @and_i32_rr(i32 %0, i32 %1) {
; X64: # %bb.0:
; X64-NEXT: movl %esi, %eax
; X64-NEXT: andl %edi, %eax
-; X64-NEXT: testl %eax, %eax
; X64-NEXT: cmovlel %edi, %eax
; X64-NEXT: retq
%3 = and i32 %1, %0
@@ -187,7 +183,6 @@ define i64 @and_i64_ri(i64 %0, i64 %1) nounwind {
; X64: # %bb.0:
; X64-NEXT: movq %rdi, %rax
; X64-NEXT: andq $-17, %rax
-; X64-NEXT: testq %rax, %rax
; X64-NEXT: cmovleq %rdi, %rax
; X64-NEXT: retq
%3 = and i64 %0, -17
@@ -223,7 +218,6 @@ define i64 @and_i64_rr(i64 %0, i64 %1) nounwind {
; X64: # %bb.0:
; X64-NEXT: movq %rsi, %rax
; X64-NEXT: andq %rdi, %rax
-; X64-NEXT: testq %rax, %rax
; X64-NEXT: cmovleq %rdi, %rax
; X64-NEXT: retq
%3 = and i64 %1, %0
diff --git a/llvm/test/CodeGen/X86/or-with-overflow.ll b/llvm/test/CodeGen/X86/or-with-overflow.ll
index c98c79dc216f..adef53c0173b 100644
--- a/llvm/test/CodeGen/X86/or-with-overflow.ll
+++ b/llvm/test/CodeGen/X86/or-with-overflow.ll
@@ -119,7 +119,6 @@ define i32 @or_i32_ri(i32 %0, i32 %1) {
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NEXT: movl %eax, %ecx
; X86-NEXT: orl $-17, %ecx
-; X86-NEXT: testl %ecx, %ecx
; X86-NEXT: jle .LBB4_2
; X86-NEXT: # %bb.1:
; X86-NEXT: movl %ecx, %eax
@@ -130,7 +129,6 @@ define i32 @or_i32_ri(i32 %0, i32 %1) {
; X64: # %bb.0:
; X64-NEXT: movl %edi, %eax
; X64-NEXT: orl $-17, %eax
-; X64-NEXT: testl %eax, %eax
; X64-NEXT: cmovlel %edi, %eax
; X64-NEXT: retq
%3 = or i32 %0, -17
@@ -145,7 +143,6 @@ define i32 @or_i32_rr(i32 %0, i32 %1) {
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-NEXT: orl %eax, %ecx
-; X86-NEXT: testl %ecx, %ecx
; X86-NEXT: jle .LBB5_2
; X86-NEXT: # %bb.1:
; X86-NEXT: movl %ecx, %eax
@@ -156,7 +153,6 @@ define i32 @or_i32_rr(i32 %0, i32 %1) {
; X64: # %bb.0:
; X64-NEXT: movl %esi, %eax
; X64-NEXT: orl %edi, %eax
-; X64-NEXT: testl %eax, %eax
; X64-NEXT: cmovlel %edi, %eax
; X64-NEXT: retq
%3 = or i32 %1, %0
@@ -190,7 +186,6 @@ define i64 @or_i64_ri(i64 %0, i64 %1) nounwind {
; X64: # %bb.0:
; X64-NEXT: movq %rdi, %rax
; X64-NEXT: orq $-17, %rax
-; X64-NEXT: testq %rax, %rax
; X64-NEXT: cmovleq %rdi, %rax
; X64-NEXT: retq
%3 = or i64 %0, -17
@@ -226,7 +221,6 @@ define i64 @or_i64_rr(i64 %0, i64 %1) nounwind {
; X64: # %bb.0:
; X64-NEXT: movq %rsi, %rax
; X64-NEXT: orq %rdi, %rax
-; X64-NEXT: testq %rax, %rax
; X64-NEXT: cmovleq %rdi, %rax
; X64-NEXT: retq
%3 = or i64 %1, %0
diff --git a/llvm/test/CodeGen/X86/xor-with-overflow.ll b/llvm/test/CodeGen/X86/xor-with-overflow.ll
index b8107e3b7127..6054c9adf5f5 100644
--- a/llvm/test/CodeGen/X86/xor-with-overflow.ll
+++ b/llvm/test/CodeGen/X86/xor-with-overflow.ll
@@ -119,7 +119,6 @@ define i32 @xor_i32_ri(i32 %0, i32 %1) {
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NEXT: movl %eax, %ecx
; X86-NEXT: xorl $-17, %ecx
-; X86-NEXT: testl %ecx, %ecx
; X86-NEXT: jle .LBB4_2
; X86-NEXT: # %bb.1:
; X86-NEXT: movl %ecx, %eax
@@ -130,7 +129,6 @@ define i32 @xor_i32_ri(i32 %0, i32 %1) {
; X64: # %bb.0:
; X64-NEXT: movl %edi, %eax
; X64-NEXT: xorl $-17, %eax
-; X64-NEXT: testl %eax, %eax
; X64-NEXT: cmovlel %edi, %eax
; X64-NEXT: retq
%3 = xor i32 %0, -17
@@ -145,7 +143,6 @@ define i32 @xor_i32_rr(i32 %0, i32 %1) {
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-NEXT: xorl %eax, %ecx
-; X86-NEXT: testl %ecx, %ecx
; X86-NEXT: jle .LBB5_2
; X86-NEXT: # %bb.1:
; X86-NEXT: movl %ecx, %eax
@@ -156,7 +153,6 @@ define i32 @xor_i32_rr(i32 %0, i32 %1) {
; X64: # %bb.0:
; X64-NEXT: movl %esi, %eax
; X64-NEXT: xorl %edi, %eax
-; X64-NEXT: testl %eax, %eax
; X64-NEXT: cmovlel %edi, %eax
; X64-NEXT: retq
%3 = xor i32 %1, %0
@@ -192,7 +188,6 @@ define i64 @xor_i64_ri(i64 %0, i64 %1) nounwind {
; X64: # %bb.0:
; X64-NEXT: movq %rdi, %rax
; X64-NEXT: xorq $-17, %rax
-; X64-NEXT: testq %rax, %rax
; X64-NEXT: cmovleq %rdi, %rax
; X64-NEXT: retq
%3 = xor i64 %0, -17
@@ -228,7 +223,6 @@ define i64 @xor_i64_rr(i64 %0, i64 %1) nounwind {
; X64: # %bb.0:
; X64-NEXT: movq %rsi, %rax
; X64-NEXT: xorq %rdi, %rax
-; X64-NEXT: testq %rax, %rax
; X64-NEXT: cmovleq %rdi, %rax
; X64-NEXT: retq
%3 = xor i64 %1, %0
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