[PATCH] D98936: [RISCV] DAG nodes and pseudo instructions for CSR access
Serge Pavlov via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Wed Apr 7 01:35:15 PDT 2021
sepavloff marked 2 inline comments as done.
sepavloff added inline comments.
================
Comment at: llvm/lib/Target/RISCV/RISCVInstrInfo.td:31
SDTCisVT<3, OtherVT>]>;
+def SDT_ReadCSR : SDTypeProfile<1, 1, [SDTCisInt<0>, SDTCisInt<1>]>;
+def SDT_WriteCSR : SDTypeProfile<0, 2, [SDTCisInt<0>, SDTCisInt<1>]>;
----------------
craig.topper wrote:
> I think this should be SDT_RISCVReadCSR to following the convention established by the others.
Renamed.
================
Comment at: llvm/lib/Target/RISCV/RISCVInstrInfo.td:1134
+ [(set GPR:$rd, (riscv_read_csr (XLenVT SR.Encoding)))]>,
+ PseudoInstExpansion<(CSRRC GPR:$rd, SR.Encoding, X0)> {
+ let hasSideEffects = 0;
----------------
craig.topper wrote:
> Should this be CSRRS to match the CSRR pseudo instruction definiton?
Changed the expansion.
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D98936/new/
https://reviews.llvm.org/D98936
More information about the llvm-commits
mailing list