[llvm] 01a23dc - [RISCV] Add an assertion to the ReplaceNodeResults handling of bitcasts to make sure the VT is always a scalar integer.

Craig Topper via llvm-commits llvm-commits at lists.llvm.org
Tue Apr 6 16:49:03 PDT 2021


Author: Craig Topper
Date: 2021-04-06T16:48:40-07:00
New Revision: 01a23dccb1a167869cb08f23817e5a885bd7b555

URL: https://github.com/llvm/llvm-project/commit/01a23dccb1a167869cb08f23817e5a885bd7b555
DIFF: https://github.com/llvm/llvm-project/commit/01a23dccb1a167869cb08f23817e5a885bd7b555.diff

LOG: [RISCV] Add an assertion to the ReplaceNodeResults handling of bitcasts to make sure the VT is always a scalar integer.

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVISelLowering.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 8bb8badf15b6..e7b0e431ab9f 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -4118,6 +4118,7 @@ void RISCVTargetLowering::ReplaceNodeResults(SDNode *N,
   }
   case ISD::BITCAST: {
     EVT VT = N->getValueType(0);
+    assert(VT.isInteger() && !VT.isVector() && "Unexpected VT!");
     SDValue Op0 = N->getOperand(0);
     EVT Op0VT = Op0.getValueType();
     MVT XLenVT = Subtarget.getXLenVT();


        


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