[PATCH] D95588: [RISCV] Implement the MC layer support of P extension

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVRegisterInfo.td:199
+
+def GPRP : RegisterClass<"RISCV",
+                         [XLenVT, XLenI8VT, XLenI16VT, XLenI32VT], 32, (add
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Jim wrote:
> craig.topper wrote:
> > Why do we need a special register class? If the size, alignment, spill size are the same, why can't we just add the types to the regular GPR class?
> I have tried to add new types to the regular GPR class before. But it show lots of `Could not infer all types in pattern!` error message on building. It have to add explicit type (XLenVT in most cases) to the existed codegen patterns which use GPR. I am not sure that is a good solution.
It's unfortunate, but it probably is the right solution since it will eliminate a special case in the assembler.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D95588/new/

https://reviews.llvm.org/D95588