[llvm] 5efe9ef - [X86] Add ANDN test case for PR48768
Simon Pilgrim via llvm-commits
llvm-commits at lists.llvm.org
Tue Apr 6 05:52:43 PDT 2021
Author: Simon Pilgrim
Date: 2021-04-06T13:52:20+01:00
New Revision: 5efe9efdadcbf635f79c9a2b19dae9a96e25496f
URL: https://github.com/llvm/llvm-project/commit/5efe9efdadcbf635f79c9a2b19dae9a96e25496f
DIFF: https://github.com/llvm/llvm-project/commit/5efe9efdadcbf635f79c9a2b19dae9a96e25496f.diff
LOG: [X86] Add ANDN test case for PR48768
D94856 covered the BMI cases where we had existing tests, this adds a missing ANDN test case
Added:
Modified:
llvm/test/CodeGen/X86/bmi.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/X86/bmi.ll b/llvm/test/CodeGen/X86/bmi.ll
index 1522d27dcec98..df6a27923b9a2 100644
--- a/llvm/test/CodeGen/X86/bmi.ll
+++ b/llvm/test/CodeGen/X86/bmi.ll
@@ -309,6 +309,28 @@ define i1 @andn_cmp_i8(i8 %x, i8 %y) {
ret i1 %cmp
}
+; FIXME: PR48768 - 'andn' clears the overflow flag, so we don't need a separate 'test'.
+define i1 @andn_cmp_i32_overflow(i32 %x, i32 %y) {
+; X86-LABEL: andn_cmp_i32_overflow:
+; X86: # %bb.0:
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: andnl {{[0-9]+}}(%esp), %eax, %eax
+; X86-NEXT: testl %eax, %eax
+; X86-NEXT: setle %al
+; X86-NEXT: retl
+;
+; X64-LABEL: andn_cmp_i32_overflow:
+; X64: # %bb.0:
+; X64-NEXT: andnl %edi, %esi, %eax
+; X64-NEXT: testl %eax, %eax
+; X64-NEXT: setle %al
+; X64-NEXT: retq
+ %noty = xor i32 %y, -1
+ %and = and i32 %x, %noty
+ %cmp = icmp slt i32 %and, 1
+ ret i1 %cmp
+}
+
declare i32 @llvm.x86.bmi.bextr.32(i32, i32)
define i32 @bextr32(i32 %x, i32 %y) {
@@ -498,10 +520,10 @@ define i32 @blsi32_z(i32 %a, i32 %b) nounwind {
; X86-LABEL: blsi32_z:
; X86: # %bb.0:
; X86-NEXT: blsil {{[0-9]+}}(%esp), %eax
-; X86-NEXT: jne .LBB24_2
+; X86-NEXT: jne .LBB25_2
; X86-NEXT: # %bb.1:
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
-; X86-NEXT: .LBB24_2:
+; X86-NEXT: .LBB25_2:
; X86-NEXT: retl
;
; X64-LABEL: blsi32_z:
@@ -605,11 +627,11 @@ define i64 @blsi64_z(i64 %a, i64 %b) nounwind {
; X86-NEXT: andl %ecx, %eax
; X86-NEXT: movl %eax, %ecx
; X86-NEXT: orl %edx, %ecx
-; X86-NEXT: jne .LBB28_2
+; X86-NEXT: jne .LBB29_2
; X86-NEXT: # %bb.1:
; X86-NEXT: movl {{[0-9]+}}(%esp), %edx
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
-; X86-NEXT: .LBB28_2:
+; X86-NEXT: .LBB29_2:
; X86-NEXT: popl %esi
; X86-NEXT: retl
;
@@ -730,10 +752,10 @@ define i32 @blsmsk32_z(i32 %a, i32 %b) nounwind {
; X86-LABEL: blsmsk32_z:
; X86: # %bb.0:
; X86-NEXT: blsmskl {{[0-9]+}}(%esp), %eax
-; X86-NEXT: jne .LBB33_2
+; X86-NEXT: jne .LBB34_2
; X86-NEXT: # %bb.1:
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
-; X86-NEXT: .LBB33_2:
+; X86-NEXT: .LBB34_2:
; X86-NEXT: retl
;
; X64-LABEL: blsmsk32_z:
@@ -835,11 +857,11 @@ define i64 @blsmsk64_z(i64 %a, i64 %b) nounwind {
; X86-NEXT: xorl %esi, %edx
; X86-NEXT: movl %eax, %ecx
; X86-NEXT: orl %edx, %ecx
-; X86-NEXT: jne .LBB37_2
+; X86-NEXT: jne .LBB38_2
; X86-NEXT: # %bb.1:
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NEXT: movl {{[0-9]+}}(%esp), %edx
-; X86-NEXT: .LBB37_2:
+; X86-NEXT: .LBB38_2:
; X86-NEXT: popl %esi
; X86-NEXT: retl
;
@@ -960,10 +982,10 @@ define i32 @blsr32_z(i32 %a, i32 %b) nounwind {
; X86-LABEL: blsr32_z:
; X86: # %bb.0:
; X86-NEXT: blsrl {{[0-9]+}}(%esp), %eax
-; X86-NEXT: jne .LBB42_2
+; X86-NEXT: jne .LBB43_2
; X86-NEXT: # %bb.1:
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
-; X86-NEXT: .LBB42_2:
+; X86-NEXT: .LBB43_2:
; X86-NEXT: retl
;
; X64-LABEL: blsr32_z:
@@ -1065,11 +1087,11 @@ define i64 @blsr64_z(i64 %a, i64 %b) nounwind {
; X86-NEXT: andl %esi, %edx
; X86-NEXT: movl %eax, %ecx
; X86-NEXT: orl %edx, %ecx
-; X86-NEXT: jne .LBB46_2
+; X86-NEXT: jne .LBB47_2
; X86-NEXT: # %bb.1:
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NEXT: movl {{[0-9]+}}(%esp), %edx
-; X86-NEXT: .LBB46_2:
+; X86-NEXT: .LBB47_2:
; X86-NEXT: popl %esi
; X86-NEXT: retl
;
@@ -1203,20 +1225,20 @@ define void @pr40060(i32, i32) {
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NEXT: bextrl %eax, {{[0-9]+}}(%esp), %eax
; X86-NEXT: testl %eax, %eax
-; X86-NEXT: js .LBB51_1
+; X86-NEXT: js .LBB52_1
; X86-NEXT: # %bb.2:
; X86-NEXT: jmp bar # TAILCALL
-; X86-NEXT: .LBB51_1:
+; X86-NEXT: .LBB52_1:
; X86-NEXT: retl
;
; X64-LABEL: pr40060:
; X64: # %bb.0:
; X64-NEXT: bextrl %esi, %edi, %eax
; X64-NEXT: testl %eax, %eax
-; X64-NEXT: js .LBB51_1
+; X64-NEXT: js .LBB52_1
; X64-NEXT: # %bb.2:
; X64-NEXT: jmp bar # TAILCALL
-; X64-NEXT: .LBB51_1:
+; X64-NEXT: .LBB52_1:
; X64-NEXT: retq
%3 = tail call i32 @llvm.x86.bmi.bextr.32(i32 %0, i32 %1)
%4 = icmp sgt i32 %3, -1
@@ -1235,10 +1257,10 @@ define i32 @blsr32_branch(i32 %x) {
; X86-NEXT: .cfi_def_cfa_offset 8
; X86-NEXT: .cfi_offset %esi, -8
; X86-NEXT: blsrl {{[0-9]+}}(%esp), %esi
-; X86-NEXT: jne .LBB52_2
+; X86-NEXT: jne .LBB53_2
; X86-NEXT: # %bb.1:
; X86-NEXT: calll bar
-; X86-NEXT: .LBB52_2:
+; X86-NEXT: .LBB53_2:
; X86-NEXT: movl %esi, %eax
; X86-NEXT: popl %esi
; X86-NEXT: .cfi_def_cfa_offset 4
@@ -1250,10 +1272,10 @@ define i32 @blsr32_branch(i32 %x) {
; X64-NEXT: .cfi_def_cfa_offset 16
; X64-NEXT: .cfi_offset %rbx, -16
; X64-NEXT: blsrl %edi, %ebx
-; X64-NEXT: jne .LBB52_2
+; X64-NEXT: jne .LBB53_2
; X64-NEXT: # %bb.1:
; X64-NEXT: callq bar
-; X64-NEXT: .LBB52_2:
+; X64-NEXT: .LBB53_2:
; X64-NEXT: movl %ebx, %eax
; X64-NEXT: popq %rbx
; X64-NEXT: .cfi_def_cfa_offset 8
@@ -1287,10 +1309,10 @@ define i64 @blsr64_branch(i64 %x) {
; X86-NEXT: andl %ecx, %edi
; X86-NEXT: movl %esi, %eax
; X86-NEXT: orl %edi, %eax
-; X86-NEXT: jne .LBB53_2
+; X86-NEXT: jne .LBB54_2
; X86-NEXT: # %bb.1:
; X86-NEXT: calll bar
-; X86-NEXT: .LBB53_2:
+; X86-NEXT: .LBB54_2:
; X86-NEXT: movl %esi, %eax
; X86-NEXT: movl %edi, %edx
; X86-NEXT: popl %esi
@@ -1305,10 +1327,10 @@ define i64 @blsr64_branch(i64 %x) {
; X64-NEXT: .cfi_def_cfa_offset 16
; X64-NEXT: .cfi_offset %rbx, -16
; X64-NEXT: blsrq %rdi, %rbx
-; X64-NEXT: jne .LBB53_2
+; X64-NEXT: jne .LBB54_2
; X64-NEXT: # %bb.1:
; X64-NEXT: callq bar
-; X64-NEXT: .LBB53_2:
+; X64-NEXT: .LBB54_2:
; X64-NEXT: movq %rbx, %rax
; X64-NEXT: popq %rbx
; X64-NEXT: .cfi_def_cfa_offset 8
@@ -1330,10 +1352,10 @@ define i32 @blsi32_branch(i32 %x) {
; X86-NEXT: .cfi_def_cfa_offset 8
; X86-NEXT: .cfi_offset %esi, -8
; X86-NEXT: blsil {{[0-9]+}}(%esp), %esi
-; X86-NEXT: jne .LBB54_2
+; X86-NEXT: jne .LBB55_2
; X86-NEXT: # %bb.1:
; X86-NEXT: calll bar
-; X86-NEXT: .LBB54_2:
+; X86-NEXT: .LBB55_2:
; X86-NEXT: movl %esi, %eax
; X86-NEXT: popl %esi
; X86-NEXT: .cfi_def_cfa_offset 4
@@ -1345,10 +1367,10 @@ define i32 @blsi32_branch(i32 %x) {
; X64-NEXT: .cfi_def_cfa_offset 16
; X64-NEXT: .cfi_offset %rbx, -16
; X64-NEXT: blsil %edi, %ebx
-; X64-NEXT: jne .LBB54_2
+; X64-NEXT: jne .LBB55_2
; X64-NEXT: # %bb.1:
; X64-NEXT: callq bar
-; X64-NEXT: .LBB54_2:
+; X64-NEXT: .LBB55_2:
; X64-NEXT: movl %ebx, %eax
; X64-NEXT: popq %rbx
; X64-NEXT: .cfi_def_cfa_offset 8
@@ -1382,10 +1404,10 @@ define i64 @blsi64_branch(i64 %x) {
; X86-NEXT: andl %eax, %edi
; X86-NEXT: movl %edi, %eax
; X86-NEXT: orl %esi, %eax
-; X86-NEXT: jne .LBB55_2
+; X86-NEXT: jne .LBB56_2
; X86-NEXT: # %bb.1:
; X86-NEXT: calll bar
-; X86-NEXT: .LBB55_2:
+; X86-NEXT: .LBB56_2:
; X86-NEXT: movl %edi, %eax
; X86-NEXT: movl %esi, %edx
; X86-NEXT: popl %esi
@@ -1400,10 +1422,10 @@ define i64 @blsi64_branch(i64 %x) {
; X64-NEXT: .cfi_def_cfa_offset 16
; X64-NEXT: .cfi_offset %rbx, -16
; X64-NEXT: blsiq %rdi, %rbx
-; X64-NEXT: jne .LBB55_2
+; X64-NEXT: jne .LBB56_2
; X64-NEXT: # %bb.1:
; X64-NEXT: callq bar
-; X64-NEXT: .LBB55_2:
+; X64-NEXT: .LBB56_2:
; X64-NEXT: movq %rbx, %rax
; X64-NEXT: popq %rbx
; X64-NEXT: .cfi_def_cfa_offset 8
@@ -1424,19 +1446,19 @@ define void @pr42118_i32(i32 %x) {
; X86-LABEL: pr42118_i32:
; X86: # %bb.0:
; X86-NEXT: blsrl {{[0-9]+}}(%esp), %eax
-; X86-NEXT: jne .LBB56_1
+; X86-NEXT: jne .LBB57_1
; X86-NEXT: # %bb.2:
; X86-NEXT: jmp bar # TAILCALL
-; X86-NEXT: .LBB56_1:
+; X86-NEXT: .LBB57_1:
; X86-NEXT: retl
;
; X64-LABEL: pr42118_i32:
; X64: # %bb.0:
; X64-NEXT: blsrl %edi, %eax
-; X64-NEXT: jne .LBB56_1
+; X64-NEXT: jne .LBB57_1
; X64-NEXT: # %bb.2:
; X64-NEXT: jmp bar # TAILCALL
-; X64-NEXT: .LBB56_1:
+; X64-NEXT: .LBB57_1:
; X64-NEXT: retq
%tmp = sub i32 0, %x
%tmp1 = and i32 %tmp, %x
@@ -1464,12 +1486,12 @@ define void @pr42118_i64(i64 %x) {
; X86-NEXT: andl %eax, %edx
; X86-NEXT: andl %ecx, %esi
; X86-NEXT: orl %edx, %esi
-; X86-NEXT: jne .LBB57_1
+; X86-NEXT: jne .LBB58_1
; X86-NEXT: # %bb.2:
; X86-NEXT: popl %esi
; X86-NEXT: .cfi_def_cfa_offset 4
; X86-NEXT: jmp bar # TAILCALL
-; X86-NEXT: .LBB57_1:
+; X86-NEXT: .LBB58_1:
; X86-NEXT: .cfi_def_cfa_offset 8
; X86-NEXT: popl %esi
; X86-NEXT: .cfi_def_cfa_offset 4
@@ -1478,10 +1500,10 @@ define void @pr42118_i64(i64 %x) {
; X64-LABEL: pr42118_i64:
; X64: # %bb.0:
; X64-NEXT: blsrq %rdi, %rax
-; X64-NEXT: jne .LBB57_1
+; X64-NEXT: jne .LBB58_1
; X64-NEXT: # %bb.2:
; X64-NEXT: jmp bar # TAILCALL
-; X64-NEXT: .LBB57_1:
+; X64-NEXT: .LBB58_1:
; X64-NEXT: retq
%tmp = sub i64 0, %x
%tmp1 = and i64 %tmp, %x
@@ -1499,11 +1521,11 @@ define i32 @blsi_cflag_32(i32 %x, i32 %y) nounwind {
; X86: # %bb.0:
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NEXT: testl %eax, %eax
-; X86-NEXT: jne .LBB58_1
+; X86-NEXT: jne .LBB59_1
; X86-NEXT: # %bb.2:
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NEXT: retl
-; X86-NEXT: .LBB58_1:
+; X86-NEXT: .LBB59_1:
; X86-NEXT: blsil %eax, %eax
; X86-NEXT: retl
;
@@ -1532,15 +1554,15 @@ define i64 @blsi_cflag_64(i64 %x, i64 %y) nounwind {
; X86-NEXT: sbbl %esi, %edx
; X86-NEXT: movl %ecx, %edi
; X86-NEXT: orl %esi, %edi
-; X86-NEXT: jne .LBB59_1
+; X86-NEXT: jne .LBB60_1
; X86-NEXT: # %bb.2:
; X86-NEXT: movl {{[0-9]+}}(%esp), %edx
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
-; X86-NEXT: jmp .LBB59_3
-; X86-NEXT: .LBB59_1:
+; X86-NEXT: jmp .LBB60_3
+; X86-NEXT: .LBB60_1:
; X86-NEXT: andl %esi, %edx
; X86-NEXT: andl %ecx, %eax
-; X86-NEXT: .LBB59_3:
+; X86-NEXT: .LBB60_3:
; X86-NEXT: popl %esi
; X86-NEXT: popl %edi
; X86-NEXT: retl
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