[PATCH] D98335: [AVR] Refactor 8-bit & 16-bit shifts

[Ben Shi via Phabricator via llvm-commits]

benshi001 added a comment.

Some key points in my design,

1. The reason for `(outs LD8:$rd)` but `(ins GPR8:$src)` in the new pseudo instructions, is that they rely on ANDI which requries R16-R31.
2. The reasons LSLW/LSRW/ASRW are not treated as LSLWN(1)/LSRWN(1)/ASRWN(1), are that 2.1 LSLW/LSRW/ASRW are important fallbacks when shiftAmount = 2, 3 2.2 LSLW/LSRW/ASRW are assisting methods for LSLWN(x)/LSRWN(x)/ASRWN(x) when shiftAmount = 5,6,9,10,13,14. They are so important that need to keep indpendent.


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  https://reviews.llvm.org/D98335/new/

https://reviews.llvm.org/D98335