[llvm] 36d4f6d - [X86] Fold xor(zext(xor(x,c1)),c2) -> xor(zext(x),xor(zext(c1),c2))

[Simon Pilgrim via llvm-commits]

Author: Simon Pilgrim
Date: 2021-04-05T11:40:37+01:00
New Revision: 36d4f6d7f8ad08bb99da544f2b6ca96e34977839

URL: https://github.com/llvm/llvm-project/commit/36d4f6d7f8ad08bb99da544f2b6ca96e34977839
DIFF: https://github.com/llvm/llvm-project/commit/36d4f6d7f8ad08bb99da544f2b6ca96e34977839.diff

LOG: [X86] Fold xor(zext(xor(x,c1)),c2) -> xor(zext(x),xor(zext(c1),c2))

Fixes PR47603 (second case) by extending rG89afec348dbd3e5078f176e978971ee2d3b5dec8

Added: 
    

Modified: 
    llvm/lib/Target/X86/X86ISelLowering.cpp
    llvm/test/CodeGen/X86/clz.ll

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 4818adb5f5903..3c81bc595eb49 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -46983,16 +46983,18 @@ static SDValue combineXor(SDNode *N, SelectionDAG &DAG,
   if (SDValue RV = foldXorTruncShiftIntoCmp(N, DAG))
     return RV;
 
+  // Fold xor(zext(xor(x,c1)),c2) -> xor(zext(x),xor(zext(c1),c2))
   // Fold xor(truncate(xor(x,c1)),c2) -> xor(truncate(x),xor(truncate(c1),c2))
   // TODO: Under what circumstances could this be performed in DAGCombine?
-  if (N->getOperand(0).getOpcode() == ISD::TRUNCATE &&
+  if ((N->getOperand(0).getOpcode() == ISD::TRUNCATE ||
+       N->getOperand(0).getOpcode() == ISD::ZERO_EXTEND) &&
       N->getOperand(0).getOperand(0).getOpcode() == N->getOpcode() &&
       isa<ConstantSDNode>(N->getOperand(1)) &&
       isa<ConstantSDNode>(N->getOperand(0).getOperand(0).getOperand(1))) {
     SDLoc DL(N);
-    SDValue TruncateSrc = N->getOperand(0).getOperand(0);
-    SDValue LHS = DAG.getNode(ISD::TRUNCATE, DL, VT, TruncateSrc.getOperand(0));
-    SDValue RHS = DAG.getNode(ISD::TRUNCATE, DL, VT, TruncateSrc.getOperand(1));
+    SDValue TruncExtSrc = N->getOperand(0).getOperand(0);
+    SDValue LHS = DAG.getZExtOrTrunc(TruncExtSrc.getOperand(0), DL, VT);
+    SDValue RHS = DAG.getZExtOrTrunc(TruncExtSrc.getOperand(1), DL, VT);
     return DAG.getNode(ISD::XOR, DL, VT, LHS,
                        DAG.getNode(ISD::XOR, DL, VT, RHS, N->getOperand(1)));
   }

diff  --git a/llvm/test/CodeGen/X86/clz.ll b/llvm/test/CodeGen/X86/clz.ll
index e11ab384c0119..f8d03362d19dc 100644
--- a/llvm/test/CodeGen/X86/clz.ll
+++ b/llvm/test/CodeGen/X86/clz.ll
@@ -1105,8 +1105,6 @@ define i32 @PR47603_zext(i32 %a0, [32 x i8]* %a1) {
 ; X64-LABEL: PR47603_zext:
 ; X64:       # %bb.0:
 ; X64-NEXT:    bsrl %edi, %eax
-; X64-NEXT:    xorl $31, %eax
-; X64-NEXT:    xorq $31, %rax
 ; X64-NEXT:    movsbl (%rsi,%rax), %eax
 ; X64-NEXT:    retq
 ;