[llvm] 67133ee - [Test] Auto-update checks in a test

[Max Kazantsev via llvm-commits]

Author: Max Kazantsev
Date: 2021-04-05T16:24:00+07:00
New Revision: 67133ee1d280230091d85a839d9a9f6665b6265f

URL: https://github.com/llvm/llvm-project/commit/67133ee1d280230091d85a839d9a9f6665b6265f
DIFF: https://github.com/llvm/llvm-project/commit/67133ee1d280230091d85a839d9a9f6665b6265f.diff

LOG: [Test] Auto-update checks in a test

Added: 
    

Modified: 
    llvm/test/Transforms/GVN/PRE/lpre-call-wrap.ll

Removed: 
    


################################################################################
diff  --git a/llvm/test/Transforms/GVN/PRE/lpre-call-wrap.ll b/llvm/test/Transforms/GVN/PRE/lpre-call-wrap.ll
index 274830549394..7c91b52088b6 100644
--- a/llvm/test/Transforms/GVN/PRE/lpre-call-wrap.ll
+++ b/llvm/test/Transforms/GVN/PRE/lpre-call-wrap.ll
@@ -1,55 +1,80 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
 ; RUN: opt -S -gvn -enable-load-pre < %s | FileCheck %s
 ;
-; Make sure the load in bb3.backedge is removed and moved into bb1 after the 
-; call.  This makes the non-call case faster. 
+; Make sure the load in bb3.backedge is removed and moved into bb1 after the
+; call.  This makes the non-call case faster.
 ;
 ; This test is derived from this C++ code (GCC PR 37810):
 ; void g();
-; struct A { 
+; struct A {
 ;   int n; int m;
 ;   A& operator++(void) { ++n; if (n == m) g(); return *this; }
-;   A() : n(0), m(0) { } 
+;   A() : n(0), m(0) { }
 ;   friend bool operator!=(A const& a1, A const& a2) { return a1.n != a2.n; }
 ; };
 ; void testfunction(A& iter) { A const end; while (iter != end) ++iter; }
 ;
 target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
 target triple = "i386-apple-darwin7"
-	%struct.A = type { i32, i32 }
+  %struct.A = type { i32, i32 }
 
 define void @_Z12testfunctionR1A(%struct.A* %iter) {
+; CHECK-LABEL: @_Z12testfunctionR1A(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[TMP0:%.*]] = getelementptr [[STRUCT_A:%.*]], %struct.A* [[ITER:%.*]], i32 0, i32 0
+; CHECK-NEXT:    [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
+; CHECK-NEXT:    [[TMP2:%.*]] = icmp eq i32 [[TMP1]], 0
+; CHECK-NEXT:    br i1 [[TMP2]], label [[RETURN:%.*]], label [[BB_NPH:%.*]]
+; CHECK:       bb.nph:
+; CHECK-NEXT:    [[TMP3:%.*]] = getelementptr [[STRUCT_A]], %struct.A* [[ITER]], i32 0, i32 1
+; CHECK-NEXT:    br label [[BB:%.*]]
+; CHECK:       bb:
+; CHECK-NEXT:    [[DOTRLE:%.*]] = phi i32 [ [[TMP1]], [[BB_NPH]] ], [ [[TMP7:%.*]], [[BB3_BACKEDGE:%.*]] ]
+; CHECK-NEXT:    [[TMP4:%.*]] = add i32 [[DOTRLE]], 1
+; CHECK-NEXT:    store i32 [[TMP4]], i32* [[TMP0]], align 4
+; CHECK-NEXT:    [[TMP5:%.*]] = load i32, i32* [[TMP3]], align 4
+; CHECK-NEXT:    [[TMP6:%.*]] = icmp eq i32 [[TMP4]], [[TMP5]]
+; CHECK-NEXT:    br i1 [[TMP6]], label [[BB1:%.*]], label [[BB3_BACKEDGE]]
+; CHECK:       bb1:
+; CHECK-NEXT:    tail call void @_Z1gv()
+; CHECK-NEXT:    [[DOTPRE:%.*]] = load i32, i32* [[TMP0]], align 4
+; CHECK-NEXT:    br label [[BB3_BACKEDGE]]
+; CHECK:       bb3.backedge:
+; CHECK-NEXT:    [[TMP7]] = phi i32 [ [[DOTPRE]], [[BB1]] ], [ [[TMP4]], [[BB]] ]
+; CHECK-NEXT:    [[TMP8:%.*]] = icmp eq i32 [[TMP7]], 0
+; CHECK-NEXT:    br i1 [[TMP8]], label [[RETURN]], label [[BB]]
+; CHECK:       return:
+; CHECK-NEXT:    ret void
+;
 entry:
-	%0 = getelementptr %struct.A, %struct.A* %iter, i32 0, i32 0		; <i32*> [#uses=3]
-	%1 = load i32, i32* %0, align 4		; <i32> [#uses=2]
-	%2 = icmp eq i32 %1, 0		; <i1> [#uses=1]
-	br i1 %2, label %return, label %bb.nph
+  %0 = getelementptr %struct.A, %struct.A* %iter, i32 0, i32 0		; <i32*> [#uses=3]
+  %1 = load i32, i32* %0, align 4		; <i32> [#uses=2]
+  %2 = icmp eq i32 %1, 0		; <i1> [#uses=1]
+  br i1 %2, label %return, label %bb.nph
 
 bb.nph:		; preds = %entry
-	%3 = getelementptr %struct.A, %struct.A* %iter, i32 0, i32 1		; <i32*> [#uses=1]
-	br label %bb
+  %3 = getelementptr %struct.A, %struct.A* %iter, i32 0, i32 1		; <i32*> [#uses=1]
+  br label %bb
 
 bb:		; preds = %bb3.backedge, %bb.nph
-	%.rle = phi i32 [ %1, %bb.nph ], [ %7, %bb3.backedge ]		; <i32> [#uses=1]
-	%4 = add i32 %.rle, 1		; <i32> [#uses=2]
-	store i32 %4, i32* %0, align 4
-	%5 = load i32, i32* %3, align 4		; <i32> [#uses=1]
-	%6 = icmp eq i32 %4, %5		; <i1> [#uses=1]
-	br i1 %6, label %bb1, label %bb3.backedge
+  %.rle = phi i32 [ %1, %bb.nph ], [ %7, %bb3.backedge ]		; <i32> [#uses=1]
+  %4 = add i32 %.rle, 1		; <i32> [#uses=2]
+  store i32 %4, i32* %0, align 4
+  %5 = load i32, i32* %3, align 4		; <i32> [#uses=1]
+  %6 = icmp eq i32 %4, %5		; <i1> [#uses=1]
+  br i1 %6, label %bb1, label %bb3.backedge
 
 bb1:		; preds = %bb
-	tail call void @_Z1gv()
-	br label %bb3.backedge
+  tail call void @_Z1gv()
+  br label %bb3.backedge
 
 bb3.backedge:		; preds = %bb, %bb1
-; CHECK: bb3.backedge:
-; CHECK-NEXT: phi
-; CHECK-NEXT: icmp
-	%7 = load i32, i32* %0, align 4		; <i32> [#uses=2]
-	%8 = icmp eq i32 %7, 0		; <i1> [#uses=1]
-	br i1 %8, label %return, label %bb
+  %7 = load i32, i32* %0, align 4		; <i32> [#uses=2]
+  %8 = icmp eq i32 %7, 0		; <i1> [#uses=1]
+  br i1 %8, label %return, label %bb
 
 return:		; preds = %bb3.backedge, %entry
-	ret void
+  ret void
 }
 
 declare void @_Z1gv()