[llvm] 4708a05 - [RISCV] Use gorciw for i32 orc.b intrinsic when Zbp is enabled.

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2021-04-04T17:14:28-07:00
New Revision: 4708a05da03038271a1a2c1cbdfe78aebfaa7afc

URL: https://github.com/llvm/llvm-project/commit/4708a05da03038271a1a2c1cbdfe78aebfaa7afc
DIFF: https://github.com/llvm/llvm-project/commit/4708a05da03038271a1a2c1cbdfe78aebfaa7afc.diff

LOG: [RISCV] Use gorciw for i32 orc.b intrinsic when Zbp is enabled.

The W version of orc.b does not exist in Zbp so we need to use
gorci encoding. If we have Zbp, we can use gorciw which can avoid a
sext.w in some cases.

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    llvm/test/CodeGen/RISCV/rv64zbb-intrinsic.ll

Removed: 
    


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diff  --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 9388300059861..75ad5b9ed3949 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -4211,7 +4211,10 @@ void RISCVTargetLowering::ReplaceNodeResults(SDNode *N,
       // Lower to the GORCI encoding for orc.b with the operand extended.
       SDValue NewOp =
           DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, N->getOperand(1));
-      SDValue Res = DAG.getNode(RISCVISD::GORCI, DL, MVT::i64, NewOp,
+      // If Zbp is enabled, use GORCIW which will sign extend the result.
+      unsigned Opc =
+          Subtarget.hasStdExtZbp() ? RISCVISD::GORCIW : RISCVISD::GORCI;
+      SDValue Res = DAG.getNode(Opc, DL, MVT::i64, NewOp,
                                 DAG.getTargetConstant(7, DL, MVT::i64));
       Results.push_back(DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Res));
       return;

diff  --git a/llvm/test/CodeGen/RISCV/rv64zbb-intrinsic.ll b/llvm/test/CodeGen/RISCV/rv64zbb-intrinsic.ll
index 262ed783a32ee..834a76eb8d7c7 100644
--- a/llvm/test/CodeGen/RISCV/rv64zbb-intrinsic.ll
+++ b/llvm/test/CodeGen/RISCV/rv64zbb-intrinsic.ll
@@ -9,8 +9,7 @@ declare i32 @llvm.riscv.orc.b.i32(i32)
 define signext i32 @orcb32(i32 signext %a) nounwind {
 ; RV64IB-LABEL: orcb32:
 ; RV64IB:       # %bb.0:
-; RV64IB-NEXT:    orc.b a0, a0
-; RV64IB-NEXT:    sext.w a0, a0
+; RV64IB-NEXT:    gorciw a0, a0, 7
 ; RV64IB-NEXT:    ret
 ;
 ; RV64IBB-LABEL: orcb32: