[llvm] 98d5db3 - [RISCV] Lower orc.b intrinsic to RISCVISD::GORCI.

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2021-04-04T12:31:41-07:00
New Revision: 98d5db3e3a3fadc4883d98388e689c1e14a2e90c

URL: https://github.com/llvm/llvm-project/commit/98d5db3e3a3fadc4883d98388e689c1e14a2e90c
DIFF: https://github.com/llvm/llvm-project/commit/98d5db3e3a3fadc4883d98388e689c1e14a2e90c.diff

LOG: [RISCV] Lower orc.b intrinsic to RISCVISD::GORCI.

This will allow us to share any future known bits, demaned bits,
or sign bits improvements.

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    llvm/lib/Target/RISCV/RISCVInstrInfoB.td

Removed: 
    


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diff  --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 46d700b45a22..938830005986 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -2810,6 +2810,10 @@ SDValue RISCVTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
     EVT PtrVT = getPointerTy(DAG.getDataLayout());
     return DAG.getRegister(RISCV::X4, PtrVT);
   }
+  case Intrinsic::riscv_orc_b:
+    // Lower to the GORCI encoding for orc.b.
+    return DAG.getNode(RISCVISD::GORCI, DL, XLenVT, Op.getOperand(1),
+                       DAG.getTargetConstant(7, DL, XLenVT));
   case Intrinsic::riscv_vmv_x_s:
     assert(Op.getValueType() == XLenVT && "Unexpected VT!");
     return DAG.getNode(RISCVISD::VMV_X_S, DL, Op.getValueType(),
@@ -4204,10 +4208,11 @@ void RISCVTargetLowering::ReplaceNodeResults(SDNode *N,
       llvm_unreachable(
           "Don't know how to custom type legalize this intrinsic!");
     case Intrinsic::riscv_orc_b: {
-      SDValue Newop1 =
+      // Lower to the GORCI encoding for orc.b with the operand extended.
+      SDValue NewOp =
           DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, N->getOperand(1));
-      SDValue Res = 
-          DAG.getNode(N->getOpcode(), DL, MVT::i64, N->getOperand(0), Newop1);
+      SDValue Res = DAG.getNode(RISCVISD::GORCI, DL, MVT::i64, NewOp,
+                                DAG.getTargetConstant(7, DL, MVT::i64));
       Results.push_back(DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Res));
       return;
     }

diff  --git a/llvm/lib/Target/RISCV/RISCVInstrInfoB.td b/llvm/lib/Target/RISCV/RISCVInstrInfoB.td
index e773f113543f..bce72b0e0275 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoB.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoB.td
@@ -17,14 +17,19 @@
 // Operand and SDNode transformation definitions.
 //===----------------------------------------------------------------------===//
 
-def riscv_clzw : SDNode<"RISCVISD::CLZW", SDTIntUnaryOp>;
-def riscv_ctzw : SDNode<"RISCVISD::CTZW", SDTIntUnaryOp>;
-def riscv_rolw : SDNode<"RISCVISD::ROLW", SDTIntShiftOp>;
-def riscv_rorw : SDNode<"RISCVISD::RORW", SDTIntShiftOp>;
-def riscv_fslw : SDNode<"RISCVISD::FSLW", SDTIntShiftDOp>;
-def riscv_fsrw : SDNode<"RISCVISD::FSRW", SDTIntShiftDOp>;
-def riscv_fsl  : SDNode<"RISCVISD::FSL",  SDTIntShiftDOp>;
-def riscv_fsr  : SDNode<"RISCVISD::FSR",  SDTIntShiftDOp>;
+def riscv_clzw   : SDNode<"RISCVISD::CLZW",   SDTIntUnaryOp>;
+def riscv_ctzw   : SDNode<"RISCVISD::CTZW",   SDTIntUnaryOp>;
+def riscv_rolw   : SDNode<"RISCVISD::ROLW",   SDTIntShiftOp>;
+def riscv_rorw   : SDNode<"RISCVISD::RORW",   SDTIntShiftOp>;
+def riscv_fslw   : SDNode<"RISCVISD::FSLW",   SDTIntShiftDOp>;
+def riscv_fsrw   : SDNode<"RISCVISD::FSRW",   SDTIntShiftDOp>;
+def riscv_fsl    : SDNode<"RISCVISD::FSL",    SDTIntShiftDOp>;
+def riscv_fsr    : SDNode<"RISCVISD::FSR",    SDTIntShiftDOp>;
+def riscv_grevi  : SDNode<"RISCVISD::GREVI",  SDTIntBinOp>;
+def riscv_greviw : SDNode<"RISCVISD::GREVIW", SDTIntBinOp>;
+def riscv_gorci  : SDNode<"RISCVISD::GORCI",  SDTIntBinOp>;
+def riscv_gorciw : SDNode<"RISCVISD::GORCIW", SDTIntBinOp>;
+def riscv_shfli  : SDNode<"RISCVISD::SHFLI",  SDTIntBinOp>;
 
 def UImmLog2XLenHalfAsmOperand : AsmOperandClass {
   let Name = "UImmLog2XLenHalf";
@@ -690,21 +695,16 @@ def : Pat<(rotr GPR:$rs1, uimmlog2xlen:$shamt),
           (RORI GPR:$rs1, uimmlog2xlen:$shamt)>;
 def : Pat<(rotl GPR:$rs1, uimmlog2xlen:$shamt),
           (RORI GPR:$rs1, (ImmSubFromXLen uimmlog2xlen:$shamt))>;
-}
 
-def riscv_grevi    : SDNode<"RISCVISD::GREVI", SDTIntBinOp, []>;
-def riscv_greviw   : SDNode<"RISCVISD::GREVIW", SDTIntBinOp, []>;
-def riscv_gorci    : SDNode<"RISCVISD::GORCI", SDTIntBinOp, []>;
-def riscv_gorciw   : SDNode<"RISCVISD::GORCIW", SDTIntBinOp, []>;
-def riscv_shfli    : SDNode<"RISCVISD::SHFLI", SDTIntBinOp, []>;
+// We treat orc.b as a separate instruction, so match it directly. We also
+// lower the Zbb orc.b intrinsic to this.
+def : Pat<(riscv_gorci GPR:$rs1, 7), (ORCB GPR:$rs1)>;
+}
 
 let Predicates = [HasStdExtZbp] in {
 def : Pat<(riscv_shfli GPR:$rs1, timm:$shamt), (SHFLI GPR:$rs1, timm:$shamt)>;
 def : Pat<(riscv_grevi GPR:$rs1, timm:$shamt), (GREVI GPR:$rs1, timm:$shamt)>;
 def : Pat<(riscv_gorci GPR:$rs1, timm:$shamt), (GORCI GPR:$rs1, timm:$shamt)>;
-
-// We treat orc.b as a separate instruction, so match it directly.
-def : Pat<(riscv_gorci GPR:$rs1, 7), (ORCB GPR:$rs1)>;
 } // Predicates = [HasStdExtZbp]
 
 let Predicates = [HasStdExtZbp, IsRV32] in {
@@ -894,10 +894,6 @@ def : Pat<(i64 (or (and (assertsexti32 GPR:$rs2), 0xFFFFFFFFFFFF0000),
           (PACKUW GPR:$rs1, GPR:$rs2)>;
 } // Predicates = [HasStdExtZbp, IsRV64]
 
-let Predicates = [HasStdExtZbb] in {
-def : PatGpr<int_riscv_orc_b, ORCB>;
-} // Predicates = [HasStdExtZbb]
-
 let Predicates = [HasStdExtZbc] in {
 def : PatGprGpr<int_riscv_clmul, CLMUL>;
 def : PatGprGpr<int_riscv_clmulh, CLMULH>;