[llvm] f78d932 - [RISCV] Add IR intrinsics for Zbc extension
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Fri Apr 2 12:09:39 PDT 2021
Author: Levy Hsu
Date: 2021-04-02T12:09:13-07:00
New Revision: f78d932cf23a6521a1f9a08c539d1a00148ebe54
URL: https://github.com/llvm/llvm-project/commit/f78d932cf23a6521a1f9a08c539d1a00148ebe54
DIFF: https://github.com/llvm/llvm-project/commit/f78d932cf23a6521a1f9a08c539d1a00148ebe54.diff
LOG: [RISCV] Add IR intrinsics for Zbc extension
Head files are included in a separate patch in case the name needs to be changed.
RV32 / 64:
clmul
clmulh
clmulr
Differential Revision: https://reviews.llvm.org/D99711
Added:
clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbc.c
clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbc.c
llvm/test/CodeGen/RISCV/rv32zbc-intrinsic.ll
llvm/test/CodeGen/RISCV/rv64zbc-intrinsic.ll
Modified:
clang/include/clang/Basic/BuiltinsRISCV.def
clang/lib/CodeGen/CGBuiltin.cpp
llvm/include/llvm/IR/IntrinsicsRISCV.td
llvm/lib/Target/RISCV/RISCVInstrInfoB.td
Removed:
################################################################################
diff --git a/clang/include/clang/Basic/BuiltinsRISCV.def b/clang/include/clang/Basic/BuiltinsRISCV.def
index 564573ffa746..e0b28011e61a 100644
--- a/clang/include/clang/Basic/BuiltinsRISCV.def
+++ b/clang/include/clang/Basic/BuiltinsRISCV.def
@@ -21,6 +21,11 @@
TARGET_BUILTIN(__builtin_riscv_orc_b_32, "ZiZi", "nc", "experimental-zbb")
TARGET_BUILTIN(__builtin_riscv_orc_b_64, "WiWi", "nc", "experimental-zbb")
+// Zbc extension
+TARGET_BUILTIN(__builtin_riscv_clmul, "LiLiLi", "nc", "experimental-zbc")
+TARGET_BUILTIN(__builtin_riscv_clmulh, "LiLiLi", "nc", "experimental-zbc")
+TARGET_BUILTIN(__builtin_riscv_clmulr, "LiLiLi", "nc", "experimental-zbc")
+
// Zbr extension
TARGET_BUILTIN(__builtin_riscv_crc32_b, "LiLi", "nc", "experimental-zbr")
TARGET_BUILTIN(__builtin_riscv_crc32_h, "LiLi", "nc", "experimental-zbr")
diff --git a/clang/lib/CodeGen/CGBuiltin.cpp b/clang/lib/CodeGen/CGBuiltin.cpp
index 899c7b944ecf..80e48fbceef4 100644
--- a/clang/lib/CodeGen/CGBuiltin.cpp
+++ b/clang/lib/CodeGen/CGBuiltin.cpp
@@ -17884,6 +17884,20 @@ Value *CodeGenFunction::EmitRISCVBuiltinExpr(unsigned BuiltinID,
IntrinsicTypes = {ResultType};
break;
+ // Zbc
+ case RISCV::BI__builtin_riscv_clmul:
+ ID = Intrinsic::riscv_clmul;
+ IntrinsicTypes = {ResultType};
+ break;
+ case RISCV::BI__builtin_riscv_clmulh:
+ ID = Intrinsic::riscv_clmulh;
+ IntrinsicTypes = {ResultType};
+ break;
+ case RISCV::BI__builtin_riscv_clmulr:
+ ID = Intrinsic::riscv_clmulr;
+ IntrinsicTypes = {ResultType};
+ break;
+
// Zbr
case RISCV::BI__builtin_riscv_crc32_b:
ID = Intrinsic::riscv_crc32_b;
diff --git a/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbc.c b/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbc.c
new file mode 100644
index 000000000000..c07bd91fb40e
--- /dev/null
+++ b/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbc.c
@@ -0,0 +1,48 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-zbc -emit-llvm %s -o - \
+// RUN: | FileCheck %s -check-prefix=RV32ZBC
+
+// RV32ZBC-LABEL: @clmul(
+// RV32ZBC-NEXT: entry:
+// RV32ZBC-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
+// RV32ZBC-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4
+// RV32ZBC-NEXT: store i32 [[A:%.*]], i32* [[A_ADDR]], align 4
+// RV32ZBC-NEXT: store i32 [[B:%.*]], i32* [[B_ADDR]], align 4
+// RV32ZBC-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
+// RV32ZBC-NEXT: [[TMP1:%.*]] = load i32, i32* [[B_ADDR]], align 4
+// RV32ZBC-NEXT: [[TMP2:%.*]] = call i32 @llvm.riscv.clmul.i32(i32 [[TMP0]], i32 [[TMP1]])
+// RV32ZBC-NEXT: ret i32 [[TMP2]]
+//
+long clmul(long a, long b) {
+ return __builtin_riscv_clmul(a, b);
+}
+
+// RV32ZBC-LABEL: @clmulh(
+// RV32ZBC-NEXT: entry:
+// RV32ZBC-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
+// RV32ZBC-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4
+// RV32ZBC-NEXT: store i32 [[A:%.*]], i32* [[A_ADDR]], align 4
+// RV32ZBC-NEXT: store i32 [[B:%.*]], i32* [[B_ADDR]], align 4
+// RV32ZBC-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
+// RV32ZBC-NEXT: [[TMP1:%.*]] = load i32, i32* [[B_ADDR]], align 4
+// RV32ZBC-NEXT: [[TMP2:%.*]] = call i32 @llvm.riscv.clmulh.i32(i32 [[TMP0]], i32 [[TMP1]])
+// RV32ZBC-NEXT: ret i32 [[TMP2]]
+//
+long clmulh(long a, long b) {
+ return __builtin_riscv_clmulh(a, b);
+}
+
+// RV32ZBC-LABEL: @clmulr(
+// RV32ZBC-NEXT: entry:
+// RV32ZBC-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
+// RV32ZBC-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4
+// RV32ZBC-NEXT: store i32 [[A:%.*]], i32* [[A_ADDR]], align 4
+// RV32ZBC-NEXT: store i32 [[B:%.*]], i32* [[B_ADDR]], align 4
+// RV32ZBC-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
+// RV32ZBC-NEXT: [[TMP1:%.*]] = load i32, i32* [[B_ADDR]], align 4
+// RV32ZBC-NEXT: [[TMP2:%.*]] = call i32 @llvm.riscv.clmulr.i32(i32 [[TMP0]], i32 [[TMP1]])
+// RV32ZBC-NEXT: ret i32 [[TMP2]]
+//
+long clmulr(long a, long b) {
+ return __builtin_riscv_clmulr(a, b);
+}
diff --git a/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbc.c b/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbc.c
new file mode 100644
index 000000000000..4dffc3aec9d2
--- /dev/null
+++ b/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbc.c
@@ -0,0 +1,48 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-zbc -emit-llvm %s -o - \
+// RUN: | FileCheck %s -check-prefix=RV64ZBC
+
+// RV64ZBC-LABEL: @clmul(
+// RV64ZBC-NEXT: entry:
+// RV64ZBC-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
+// RV64ZBC-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
+// RV64ZBC-NEXT: store i64 [[A:%.*]], i64* [[A_ADDR]], align 8
+// RV64ZBC-NEXT: store i64 [[B:%.*]], i64* [[B_ADDR]], align 8
+// RV64ZBC-NEXT: [[TMP0:%.*]] = load i64, i64* [[A_ADDR]], align 8
+// RV64ZBC-NEXT: [[TMP1:%.*]] = load i64, i64* [[B_ADDR]], align 8
+// RV64ZBC-NEXT: [[TMP2:%.*]] = call i64 @llvm.riscv.clmul.i64(i64 [[TMP0]], i64 [[TMP1]])
+// RV64ZBC-NEXT: ret i64 [[TMP2]]
+//
+long clmul(long a, long b) {
+ return __builtin_riscv_clmul(a, b);
+}
+
+// RV64ZBC-LABEL: @clmulh(
+// RV64ZBC-NEXT: entry:
+// RV64ZBC-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
+// RV64ZBC-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
+// RV64ZBC-NEXT: store i64 [[A:%.*]], i64* [[A_ADDR]], align 8
+// RV64ZBC-NEXT: store i64 [[B:%.*]], i64* [[B_ADDR]], align 8
+// RV64ZBC-NEXT: [[TMP0:%.*]] = load i64, i64* [[A_ADDR]], align 8
+// RV64ZBC-NEXT: [[TMP1:%.*]] = load i64, i64* [[B_ADDR]], align 8
+// RV64ZBC-NEXT: [[TMP2:%.*]] = call i64 @llvm.riscv.clmulh.i64(i64 [[TMP0]], i64 [[TMP1]])
+// RV64ZBC-NEXT: ret i64 [[TMP2]]
+//
+long clmulh(long a, long b) {
+ return __builtin_riscv_clmulh(a, b);
+}
+
+// RV64ZBC-LABEL: @clmulr(
+// RV64ZBC-NEXT: entry:
+// RV64ZBC-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
+// RV64ZBC-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
+// RV64ZBC-NEXT: store i64 [[A:%.*]], i64* [[A_ADDR]], align 8
+// RV64ZBC-NEXT: store i64 [[B:%.*]], i64* [[B_ADDR]], align 8
+// RV64ZBC-NEXT: [[TMP0:%.*]] = load i64, i64* [[A_ADDR]], align 8
+// RV64ZBC-NEXT: [[TMP1:%.*]] = load i64, i64* [[B_ADDR]], align 8
+// RV64ZBC-NEXT: [[TMP2:%.*]] = call i64 @llvm.riscv.clmulr.i64(i64 [[TMP0]], i64 [[TMP1]])
+// RV64ZBC-NEXT: ret i64 [[TMP2]]
+//
+long clmulr(long a, long b) {
+ return __builtin_riscv_clmulr(a, b);
+}
diff --git a/llvm/include/llvm/IR/IntrinsicsRISCV.td b/llvm/include/llvm/IR/IntrinsicsRISCV.td
index dc18b2278a54..fa005c98f11d 100644
--- a/llvm/include/llvm/IR/IntrinsicsRISCV.td
+++ b/llvm/include/llvm/IR/IntrinsicsRISCV.td
@@ -76,10 +76,19 @@ let TargetPrefix = "riscv" in {
: Intrinsic<[llvm_any_ty],
[LLVMMatchType<0>],
[IntrNoMem, IntrSpeculatable, IntrWillReturn]>;
+ class BitManipGPRGPRIntrinsics
+ : Intrinsic<[llvm_any_ty],
+ [LLVMMatchType<0>, LLVMMatchType<0>],
+ [IntrNoMem, IntrSpeculatable, IntrWillReturn]>;
// Zbb
def int_riscv_orc_b : BitManipGPRIntrinsics;
+ // Zbc
+ def int_riscv_clmul : BitManipGPRGPRIntrinsics;
+ def int_riscv_clmulh : BitManipGPRGPRIntrinsics;
+ def int_riscv_clmulr : BitManipGPRGPRIntrinsics;
+
// Zbr
def int_riscv_crc32_b : BitManipGPRIntrinsics;
def int_riscv_crc32_h : BitManipGPRIntrinsics;
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoB.td b/llvm/lib/Target/RISCV/RISCVInstrInfoB.td
index db62edc07fe7..0b194064f997 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoB.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoB.td
@@ -898,6 +898,12 @@ let Predicates = [HasStdExtZbb] in {
def : PatGpr<int_riscv_orc_b, ORCB>;
} // Predicates = [HasStdExtZbb]
+let Predicates = [HasStdExtZbc] in {
+def : PatGprGpr<int_riscv_clmul, CLMUL>;
+def : PatGprGpr<int_riscv_clmulh, CLMULH>;
+def : PatGprGpr<int_riscv_clmulr, CLMULR>;
+} // Predicates = [HasStdExtZbc]
+
let Predicates = [HasStdExtZbr] in {
def : PatGpr<int_riscv_crc32_b, CRC32B>;
def : PatGpr<int_riscv_crc32_h, CRC32H>;
diff --git a/llvm/test/CodeGen/RISCV/rv32zbc-intrinsic.ll b/llvm/test/CodeGen/RISCV/rv32zbc-intrinsic.ll
new file mode 100644
index 000000000000..2954a65796a2
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rv32zbc-intrinsic.ll
@@ -0,0 +1,53 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-b -verify-machineinstrs < %s \
+; RUN: | FileCheck %s -check-prefix=RV32IB
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbc -verify-machineinstrs < %s \
+; RUN: | FileCheck %s -check-prefix=RV32IBC
+
+declare i32 @llvm.riscv.clmul.i32(i32 %a, i32 %b)
+
+define i32 @clmul32(i32 %a, i32 %b) nounwind {
+; RV32IB-LABEL: clmul32:
+; RV32IB: # %bb.0:
+; RV32IB-NEXT: clmul a0, a0, a1
+; RV32IB-NEXT: ret
+;
+; RV32IBC-LABEL: clmul32:
+; RV32IBC: # %bb.0:
+; RV32IBC-NEXT: clmul a0, a0, a1
+; RV32IBC-NEXT: ret
+ %tmp = call i32 @llvm.riscv.clmul.i32(i32 %a, i32 %b)
+ ret i32 %tmp
+}
+
+declare i32 @llvm.riscv.clmulh.i32(i32 %a, i32 %b)
+
+define i32 @clmul32h(i32 %a, i32 %b) nounwind {
+; RV32IB-LABEL: clmul32h:
+; RV32IB: # %bb.0:
+; RV32IB-NEXT: clmulh a0, a0, a1
+; RV32IB-NEXT: ret
+;
+; RV32IBC-LABEL: clmul32h:
+; RV32IBC: # %bb.0:
+; RV32IBC-NEXT: clmulh a0, a0, a1
+; RV32IBC-NEXT: ret
+ %tmp = call i32 @llvm.riscv.clmulh.i32(i32 %a, i32 %b)
+ ret i32 %tmp
+}
+
+declare i32 @llvm.riscv.clmulr.i32(i32 %a, i32 %b)
+
+define i32 @clmul32r(i32 %a, i32 %b) nounwind {
+; RV32IB-LABEL: clmul32r:
+; RV32IB: # %bb.0:
+; RV32IB-NEXT: clmulr a0, a0, a1
+; RV32IB-NEXT: ret
+;
+; RV32IBC-LABEL: clmul32r:
+; RV32IBC: # %bb.0:
+; RV32IBC-NEXT: clmulr a0, a0, a1
+; RV32IBC-NEXT: ret
+ %tmp = call i32 @llvm.riscv.clmulr.i32(i32 %a, i32 %b)
+ ret i32 %tmp
+}
diff --git a/llvm/test/CodeGen/RISCV/rv64zbc-intrinsic.ll b/llvm/test/CodeGen/RISCV/rv64zbc-intrinsic.ll
new file mode 100644
index 000000000000..840216725ad8
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rv64zbc-intrinsic.ll
@@ -0,0 +1,53 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-b -verify-machineinstrs < %s \
+; RUN: | FileCheck %s -check-prefix=RV64IB
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbc -verify-machineinstrs < %s \
+; RUN: | FileCheck %s -check-prefix=RV64IBC
+
+declare i64 @llvm.riscv.clmul.i64(i64 %a, i64 %b)
+
+define i64 @clmul64(i64 %a, i64 %b) nounwind {
+; RV64IB-LABEL: clmul64:
+; RV64IB: # %bb.0:
+; RV64IB-NEXT: clmul a0, a0, a1
+; RV64IB-NEXT: ret
+;
+; RV64IBC-LABEL: clmul64:
+; RV64IBC: # %bb.0:
+; RV64IBC-NEXT: clmul a0, a0, a1
+; RV64IBC-NEXT: ret
+ %tmp = call i64 @llvm.riscv.clmul.i64(i64 %a, i64 %b)
+ ret i64 %tmp
+}
+
+declare i64 @llvm.riscv.clmulh.i64(i64 %a, i64 %b)
+
+define i64 @clmul64h(i64 %a, i64 %b) nounwind {
+; RV64IB-LABEL: clmul64h:
+; RV64IB: # %bb.0:
+; RV64IB-NEXT: clmulh a0, a0, a1
+; RV64IB-NEXT: ret
+;
+; RV64IBC-LABEL: clmul64h:
+; RV64IBC: # %bb.0:
+; RV64IBC-NEXT: clmulh a0, a0, a1
+; RV64IBC-NEXT: ret
+ %tmp = call i64 @llvm.riscv.clmulh.i64(i64 %a, i64 %b)
+ ret i64 %tmp
+}
+
+declare i64 @llvm.riscv.clmulr.i64(i64 %a, i64 %b)
+
+define i64 @clmul64r(i64 %a, i64 %b) nounwind {
+; RV64IB-LABEL: clmul64r:
+; RV64IB: # %bb.0:
+; RV64IB-NEXT: clmulr a0, a0, a1
+; RV64IB-NEXT: ret
+;
+; RV64IBC-LABEL: clmul64r:
+; RV64IBC: # %bb.0:
+; RV64IBC-NEXT: clmulr a0, a0, a1
+; RV64IBC-NEXT: ret
+ %tmp = call i64 @llvm.riscv.clmulr.i64(i64 %a, i64 %b)
+ ret i64 %tmp
+}
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