[llvm] 1addc23 - [MC][ARM] add .w suffixes for ORN/ORNS T1

[Nick Desaulniers via llvm-commits]

Author: Nick Desaulniers
Date: 2021-04-01T10:27:09-07:00
New Revision: 1addc231cd5b948012c3c07ad0f6b671a0793e55

URL: https://github.com/llvm/llvm-project/commit/1addc231cd5b948012c3c07ad0f6b671a0793e55
DIFF: https://github.com/llvm/llvm-project/commit/1addc231cd5b948012c3c07ad0f6b671a0793e55.diff

LOG: [MC][ARM] add .w suffixes for ORN/ORNS T1

See also:
F5.1.128 ORN, ORNS (register) T1 shift or rotate by value variant
of the Arm ARM.

Link: https://github.com/ClangBuiltLinux/linux/issues/1309

Reviewed By: DavidSpickett

Differential Revision: https://reviews.llvm.org/D99538

Added: 
    

Modified: 
    llvm/lib/Target/ARM/ARMInstrThumb2.td
    llvm/test/MC/ARM/basic-thumb2-instructions.s

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/ARM/ARMInstrThumb2.td b/llvm/lib/Target/ARM/ARMInstrThumb2.td
index 04d3bd8e5e12f..bc772f35b5b30 100644
--- a/llvm/lib/Target/ARM/ARMInstrThumb2.td
+++ b/llvm/lib/Target/ARM/ARMInstrThumb2.td
@@ -2849,6 +2849,12 @@ let Constraints = "$src = $Rd" in {
 defm t2ORN  : T2I_bin_irs<0b0011, "orn",
                           IIC_iBITi, IIC_iBITr, IIC_iBITsi,
                           BinOpFrag<(or node:$LHS, (not node:$RHS))>, 0, "">;
+def : t2InstAlias<"orn${s}${p}.w $Rd, $Rn, $imm",
+   (t2ORNri rGPR:$Rd, rGPR:$Rn, t2_so_imm:$imm, pred:$p, cc_out:$s)>;
+def : t2InstAlias<"orn${s}${p}.w $Rd, $Rn, $Rm",
+   (t2ORNrr rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, pred:$p, cc_out:$s)>;
+def : t2InstAlias<"orn${s}${p}.w $Rd, $Rn, $ShiftedRm",
+   (t2ORNrs rGPR:$Rd, rGPR:$Rn, t2_so_reg:$ShiftedRm, pred:$p, cc_out:$s)>;
 
 /// T2I_un_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for a
 /// unary operation that produces a value. These are predicable and can be

diff  --git a/llvm/test/MC/ARM/basic-thumb2-instructions.s b/llvm/test/MC/ARM/basic-thumb2-instructions.s
index 5395a0bcbef00..636067a6f37be 100644
--- a/llvm/test/MC/ARM/basic-thumb2-instructions.s
+++ b/llvm/test/MC/ARM/basic-thumb2-instructions.s
@@ -1877,17 +1877,25 @@ adds sp, #-4096
 @ ORN
 @------------------------------------------------------------------------------
         orn r4, r5, #0xf000
+        orn.w r4, r5, #0xf000
         orn r4, r5, r6
+        orn.w r4, r5, r6
         orns r4, r5, r6
+        orns.w r4, r5, r6
         orn r4, r5, r6, lsl #5
+        orn.w r4, r5, r6, lsl #5
         orns r4, r5, r6, lsr #5
         orn r4, r5, r6, lsr #5
         orns r4, r5, r6, asr #5
         orn r4, r5, r6, ror #5
 
 @ CHECK: orn	r4, r5, #61440          @ encoding: [0x65,0xf4,0x70,0x44]
+@ CHECK: orn	r4, r5, #61440          @ encoding: [0x65,0xf4,0x70,0x44]
+@ CHECK: orn	r4, r5, r6              @ encoding: [0x65,0xea,0x06,0x04]
 @ CHECK: orn	r4, r5, r6              @ encoding: [0x65,0xea,0x06,0x04]
 @ CHECK: orns	r4, r5, r6              @ encoding: [0x75,0xea,0x06,0x04]
+@ CHECK: orns	r4, r5, r6              @ encoding: [0x75,0xea,0x06,0x04]
+@ CHECK: orn	r4, r5, r6, lsl #5      @ encoding: [0x65,0xea,0x46,0x14]
 @ CHECK: orn	r4, r5, r6, lsl #5      @ encoding: [0x65,0xea,0x46,0x14]
 @ CHECK: orns	r4, r5, r6, lsr #5      @ encoding: [0x75,0xea,0x56,0x14]
 @ CHECK: orn	r4, r5, r6, lsr #5      @ encoding: [0x65,0xea,0x56,0x14]