[PATCH] D98936: [RISCV] DAG nodes and pseudo instructions for CSR access

[Evandro Menezes via Phabricator via llvm-commits]

evandro added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVInstrInfo.td:1168
+    PseudoInstExpansion<(CSRRC GPR:$rd, SR.Encoding, X0)> {
+  let hasSideEffects = 0;
+  let Uses = Regs;
----------------
Methinks that `hasSideEffects = 0` is fine for reading CSRs, but not sure that there's some weird register out there that changes state after being read.


================
Comment at: llvm/lib/Target/RISCV/RISCVInstrInfo.td:1176
+    PseudoInstExpansion<(CSRRW X0, SR.Encoding, GPR:$val)> {
+  let hasSideEffects = 0;
+  let Defs = Regs;
----------------
This should definitely be `hasSideEffects = 1`.


================
Comment at: llvm/lib/Target/RISCV/RISCVInstrInfo.td:1184
+    PseudoInstExpansion<(CSRRW GPR:$rd, SR.Encoding, GPR:$val)> {
+  let hasSideEffects = 0;
+  let Uses = Regs;
----------------
As should this be `hasSideEffects = 1` too.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D98936/new/

https://reviews.llvm.org/D98936