[PATCH] D99586: [AArch64] Default to zero-cycle-zeroing FP registers.

[Sjoerd Meijer via Phabricator via llvm-commits]

SjoerdMeijer updated this revision to Diff 334694.
SjoerdMeijer edited the summary of this revision.
SjoerdMeijer added a comment.

Adjust this to D99710 <https://reviews.llvm.org/D99710>, that uses movi d0 that zeros 64 bits and not 128 bits, which enables this as a default for all cores.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D99586/new/

https://reviews.llvm.org/D99586

Files:
  llvm/lib/Target/AArch64/AArch64.td
  llvm/lib/Target/AArch64/AArch64Subtarget.h
  llvm/test/CodeGen/AArch64/arm64-fast-isel-materialize.ll
  llvm/test/CodeGen/AArch64/arm64-fp-contract-zero.ll
  llvm/test/CodeGen/AArch64/arm64-rev.ll
  llvm/test/CodeGen/AArch64/arm64-zero-cycle-zeroing.ll
  llvm/test/CodeGen/AArch64/f16-imm.ll
  llvm/test/CodeGen/AArch64/fptosi-sat-scalar.ll
  llvm/test/CodeGen/AArch64/fptosi-sat-vector.ll
  llvm/test/CodeGen/AArch64/fptoui-sat-scalar.ll
  llvm/test/CodeGen/AArch64/fptoui-sat-vector.ll
  llvm/test/CodeGen/AArch64/remat-float0.ll

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