[PATCH] D99730: [RISCV] Optimize more redundant VSETVLIs

[Fraser Cormack via Phabricator via llvm-commits]

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D99717 <https://reviews.llvm.org/D99717> introduced some test cases which showed that the output of one
vsetvli into another would not be picked up by the RISCVCleanupVSETVLI
pass. This patch teaches the optimization about such a pattern. The
pattern is quite common when using the RVV vsetvli intrinsic to pass the
VL onto other intrinsics.

The second test case introduced by D99717 <https://reviews.llvm.org/D99717> is left unoptimized by this
patch. It is a rarer case and will require us to rewire any uses of the
redundant vset[i]vli's output to the previous one's.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D99730

Files:
  llvm/lib/Target/RISCV/RISCVCleanupVSETVLI.cpp
  llvm/test/CodeGen/RISCV/rvv/cleanup-vsetvli.mir
  llvm/test/CodeGen/RISCV/rvv/rv32-vsetvli-intrinsics.ll
  llvm/test/CodeGen/RISCV/rvv/rv64-vsetvli-intrinsics.ll

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