[PATCH] D98821: [RISCV] Improve 64-bit integer materialization for some cases.

[Alex Bradbury via Phabricator via llvm-commits]

asb accepted this revision.
asb added a comment.
This revision is now accepted and ready to land.

LGTM, left a couple of nits on comment typos. Thanks!



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Comment at: llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.cpp:88
+    Val <<= ShiftAmount;
+    // Fill in the bits that will be shifted out with 1s. And example where
+    // this helps is trailing one masks with 32 or more ones. This will generate
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"And example" => "An example"


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Comment at: llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.h:29
 // immediate value into a register. A sequence of instructions represented by
 // a simple struct produced rather than directly emitting the instructions in
 // order to allow this helper to be used from both the MC layer and during
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Pre-existing typo you might fix while editing this: "produced" => "is produced".



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  https://reviews.llvm.org/D98821/new/

https://reviews.llvm.org/D98821