[llvm] f7aeace - [X86][SSE] Add isHorizOp helper function. NFCI.
Simon Pilgrim via llvm-commits
llvm-commits at lists.llvm.org
Thu Apr 1 03:54:22 PDT 2021
Author: Simon Pilgrim
Date: 2021-04-01T11:54:09+01:00
New Revision: f7aeaced658c507c5d5ac6e589f4844588267eef
URL: https://github.com/llvm/llvm-project/commit/f7aeaced658c507c5d5ac6e589f4844588267eef
DIFF: https://github.com/llvm/llvm-project/commit/f7aeaced658c507c5d5ac6e589f4844588267eef.diff
LOG: [X86][SSE] Add isHorizOp helper function. NFCI.
Added:
Modified:
llvm/lib/Target/X86/X86ISelLowering.cpp
Removed:
################################################################################
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 8c128c9e19b85..0cd63d69c0501 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -9209,6 +9209,19 @@ static SDValue LowerBUILD_VECTORvXi1(SDValue Op, SelectionDAG &DAG,
return DstVec;
}
+static bool isHorizOp(unsigned Opcode) {
+ switch (Opcode) {
+ case X86ISD::PACKSS:
+ case X86ISD::PACKUS:
+ case X86ISD::FHADD:
+ case X86ISD::FHSUB:
+ case X86ISD::HADD:
+ case X86ISD::HSUB:
+ return true;
+ }
+ return false;
+}
+
/// This is a helper function of LowerToHorizontalOp().
/// This function checks that the build_vector \p N in input implements a
/// 128-bit partial horizontal operation on a 256-bit vector, but that operation
@@ -43295,10 +43308,7 @@ static SDValue combineShiftRightLogical(SDNode *N, SelectionDAG &DAG,
static SDValue combineHorizOpWithShuffle(SDNode *N, SelectionDAG &DAG,
const X86Subtarget &Subtarget) {
unsigned Opcode = N->getOpcode();
- assert((X86ISD::HADD == Opcode || X86ISD::FHADD == Opcode ||
- X86ISD::HSUB == Opcode || X86ISD::FHSUB == Opcode ||
- X86ISD::PACKSS == Opcode || X86ISD::PACKUS == Opcode) &&
- "Unexpected hadd/hsub/pack opcode");
+ assert(isHorizOp(Opcode) && "Unexpected hadd/hsub/pack opcode");
EVT VT = N->getValueType(0);
SDValue N0 = N->getOperand(0);
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