[PATCH] D99635: [SelectionDAG] Add extra check on asm operand legalization.

[Matt Arsenault via Phabricator via llvm-commits]

arsenm requested changes to this revision.
arsenm added a comment.
This revision now requires changes to proceed.

Missing test



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Comment at: llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp:8190-8191
          OpInfo.Type == InlineAsm::isInput) &&
-        !TRI.isTypeLegalForClass(*RC, OpInfo.ConstraintVT)) {
+        (!TLI.isTypeLegal(OpInfo.ConstraintVT) ||
+         !TRI.isTypeLegalForClass(*RC, OpInfo.ConstraintVT))) {
       // Try to convert to the first EVT that the reg class contains.  If the
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I'm not sure I see what case this fixes exactly. The concept of type legality is so convoluted already.


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Comment at: llvm/lib/Target/AMDGPU/SIRegisterInfo.td:812
 defm VReg_96 : VRegClass<3, [v3i32, v3f32], (add VGPR_96)>;
-defm VReg_128 : VRegClass<4, [v4i32, v4f32, v2i64, v2f64], (add VGPR_128)>;
+defm VReg_128 : VRegClass<4, [v4i32, v4f32, v2i64, v2f64, i128], (add VGPR_128)>;
 defm VReg_160 : VRegClass<5, [v5i32, v5f32], (add VGPR_160)>;
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This is a separate change. All of the test changes are GLobalISel, and only from this part


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D99635/new/

https://reviews.llvm.org/D99635