[PATCH] D99320: [RISCV] [1/2] Add intrinsic for Zbb extension

Craig Topper via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Wed Mar 31 09:18:43 PDT 2021


craig.topper added a comment.

In D99320#2661285 <https://reviews.llvm.org/D99320#2661285>, @asb wrote:

> Can I just check the reasoning on the naming? I see that the bitmanip 0.93 spec proposes `_{rv,rv32,rv64}_{opname}` intrinsics. Does the `__builtin__{riscv,riscv32,riscv64}_opname` format match what GCC are doing / planning to do here? Precedent for RVV, for other archs, or something else?
>
> Just trying to determine to what these names are an open item of discussion vs matching something else.
>
> EDIT: I see Craig commented on this point in https://reviews.llvm.org/D99009#2660456

Yeah the big open for naming is the name of the intrinsic header. Whether it should be rvintrin.h or riscv_intrinsic.h.

The builtins in this patch are

__builtin_riscv_orc_b_32
__builtin_riscv_orc_b_64

I've update the description summary to reflect this since it change during development.

The Zbr patch uses the following without a 32/64 suffix.
__builtin_riscv_crc32_b/w/d/q

There's a difference because orc.b needs to be available for 32-bit on RV32 and RV64 per the spec so we have two builtins. crc32.b intrinsics in the spec are defined only for xlen so we have a single builtin.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D99320/new/

https://reviews.llvm.org/D99320



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